A Novel Thermal Position Sensor Integrated On A Plastic Substrate

Microelectromechanical systems (MEMS), printed-circuit board (PCB), Temperature detection, motion sensorA thermal position sensor was fabricated and evaluated. The device consists of an array of temperature sensing elements, fabricated entirely on a plastic substrate. A novel fabrication technology was implemented which allows direct integration with read out electronics and communication to the macro-world without the use of wire bonding. The fabricated sensing elements are temperature sensitive Pt resistors with an average TCR of 0.0024/C. The device realizes the detection of the position and the motion of a heating source by monitoring the resistance variation of the thermistor array. The application field of such a cost-effective position sensor is considered quite extensive

Leakage current and charging/discharging processes in barrier-type anodic alumina thin films for use in metal-insulator-metal capacitors

Barrier-type anodic alumina thin films are interesting for use in high capacitance density metal-insulator-metal capacitors due to their excellent dielectric properties at small thickness. This thickness is easily controlled by the anodization voltage. In previous papers we studied the main parameters of interest of the Al/barrier-type anodic alumina/Al structure for use in RF applications and showed the great potential of barrier-type anodic alumina in this respect. In this paper, we investigated in detail charging/discharging processes and leakage current of the above dielectric material. Two different sets of metal-insulator-metal capacitors were studied, namely, with the top Al electrode being either e-gun deposited or sputtered. The dielectric constant of the barrier-type anodic alumina was found at 9.3. Low leakage current was observed in all samples studied. Furthermore, depending on the film thickness, field emission following the Fowler-Nordheim mechanism was observed above an applied electric field. Charging of the anodic dielectric was observed, occurring in the bulk of the anodic layer. The stored charge was of the order of few μC/cm2 and the calculated trap density ∼2 × 1018 states/cm3, the most probable origin of charge traps being, in our opinion, positive electrolyte ions trapped in the dielectric during anodization. We do not think that oxygen vacancies play an important role, since their existence would have a more important impact on the leakage current characteristics, such as resistive memory effects or significant changes during annealing, which were not observed. Finally, discharging characteristic times as high as 5 × 109 s were measured. © 2018 Author(s)

Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics

International audienceThree-dimensional (3D) Si surface nanostructuring is interesting towards increasing the capacitance density of a metal-oxidesemiconductor (MOS) capacitor, while keeping reduced footprint for miniaturization. Si nanowires (SiNWs) can be used in this respect. With the aim of understanding the electrical versus geometrical characteristics of such capacitors, we fabricated and studied a MOS capacitor with highly ordered arrays of vertical Si nanowires of different lengths and thermal silicon oxide dielectric, in comparison to similar flat MOS capacitors. The high homogeneity and ordering of the SiNWs allowed the determination of the single SiNW capacitance and intrinsic series resistance, as well as other electrical characteristics (density of interface states, flat-band voltage and leakage current) in relation to the geometrical characteristics of the SiNWs. The SiNW capacitors demonstrated increased capacitance density compared to the flat case, while maintaining a cutoff frequency above 1 MHz, much higher than in other reports in the literature. Finally, our model system has been shown to constitute an excellent platform for the study of SiNW capacitors with either grown or deposited dielectrics, as for example high-k dielectrics for further increasing the capacitance density. This will be the subject of future work

Energy transfer in aggregated CuInS2/ZnS core-shell quantum dots deposited as solid films

We report on the morphology and optical properties of CuInS2/ZnS core-shell quantum dots in solid films by means of AFM, SEM, HRTEM, steady state and time-resolved photoluminescence (PL) spectroscopy. The amount of aggregation of the CuInS2/ZnS QDs was controlled by changing the preparation conditions of the films. A red-shift of the PL spectrum of CuInS2/ZnS core-shell quantum dots, deposited as solid films on silicon substrates, is observed upon increasing the amount of aggregation. The presence of larger aggregates was found to lead to a larger PL red-shift. Besides, as the degree of aggregation increased, the PL decay became slower. We attribute the observed PL red-shift to energy transfer from the smaller to the larger dots within the aggregates, with the emission being realized via a long decay recombination mechanism (100-200 ns), the origin of which is discussed. © 2016 IOP Publishing Ltd

Improved surface-enhanced-raman scattering sensitivity using si nanowires/silver nanostructures by a single step metal-assisted chemical etching

In this study, we developed highly sensitive substrates for Surface-Enhanced-Raman-Scattering (SERS) spectroscopy, consisting of silicon nanowires (SiNWs) decorated by silver nanos-tructures using single-step Metal Assisted Chemical Etching (MACE). One-step MACE was per-formed on p-type Si substrates by immersion in AgNO3 /HF aqueous solutions resulting in the formation of SiNWs decorated by either silver aggregates or dendrites. Specifically, dendrites were formed during SiNWs’ growth in the etchant solution, whereas aggregates were grown after the removal of the dendrites from the SiNWs in HNO3 aqueous solution and subsequent re-immersion of the specimens in a AgNO3 /HF aqueous solution by adjusting the growth time to achieve the desired density of silver nanostructures. The dendrites had much larger height than the aggregates. R6G was used as analyte to test the SERS activity of the substrates prepared by the two fabrication processes. The silver aggregates showed a considerably lower limit of detection (LOD) for SERS down to a R6G concentration of 10−13 M, and much better uniformity in terms of detection in comparison with the silver dendritic structures. Enhancement factors in the range 105 –1010 were calculated, demonstrating very high SERS sensitivities for analytic applications. © 2021 by the authors. Licensee MDPI, Basel, Switzerland

Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si

In this work, two novel RF substrate technologies are compared, namely local porous Si RF substrate technology and high resistivity Si with a trap-rich layer on top (trap-rich HR-Si). Using standard Si processing, identical co-planar waveguide transmission lines and test inductors were fabricated on the above two substrates, as well as on quartz and on standard p-type Si. Broadband electrical characterization in the frequency range from 40 MHz to 40 GHz revealed that porous Si substrate provides much higher effective resistivity and lower dielectric constant than trap-rich HR-Si, actually comparable with quartz substrate values. Lower dielectric constant leads to drastic reduction of crosstalk and provides design options for higher characteristic impedance devices. Higher effective substrate resistivity leads to lower attenuation losses and reduced non-linearities, as well as better quality factor for both transmission lines and inductors. Porous Si, which is CMOS-compatible and cost-efficient, demonstrates state-of-the-art RF performances comparable with quartz substrate. © 2013 Elsevier Ltd. All rights reserved

Effect of temperature on advanced Si-based substrates performance for RF passive integration

This paper analyses RF substrate losses and non-linearity on Si-based substrates. Through measurements it is shown that trap-rich high resistivity silicon and porous silicon substrates are virtually lossless up to 120 °C. Although, RF losses and CPW attenuation increases with temperature on both Si-based solutions, they remain acceptable for high temperature RF applications. Porous locally grown silicon shows better linearity than a comparable trap-rich high-resistivity (HR) Si substrate up to 175°C. Both Si-based solutions are considered as promising substrates for RF integration and system-on-chip applications. © 2013 Elsevier B.V. All rights reserved