Study of dynamics of charge trapping in a-Si:H/SiN TFTs

In this paper we present the study of the failure mechanism responsible for long-term degradation that ultimately leads to instability in a-Si:H/SiN TFTs. The experimental data points we obtain by monitoring in-situ the drain current during gate bias stress (forward and reverse bias) and relaxation could not be fitted with the models existent in the literature. A new model that we have christened "Progressive Degradation Model" (PDM) emerged. The model makes use of Heimann-Warfield theory of trapping/detrapping front. PDM achieves a consistent fit to any bias condition showing that the degradation can be modelled quantitatively yielding the number of traps involved, their position and the charge dispersion coefficient. According to PDM the degradation of electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites in a-SiN:H transitional region

Dynamics of metastable defects in a-Si:H/SiN TFTs

This paper has aimed at creating a more complete picture about the instability mechanism responsible for a-Si:H/SiN TFTs degradation. Additional insight about the degradation kinetics in a-Si:H/SiN TFTs is obtained by the in-situ monitoring of the source to drain current during alternative periods of stress and relaxation. The results presented in this paper come to the conclusion that the physical mechanism responsible for instability of the device operating at low bias stress, short stress time and different temperatures is a combination of defect creation and the trapping/detrapping of the carriers

Determination of the contribution of defect creation and charge trapping to the degradation of a-Si:H/SiN TFTs at room temperature and low voltages

In this paper is presented a qualitative investigation upon the mechanisms that cause the shift of the electrical parameters in thin film transistors (TFT). The transistors are made of amorphous hydrogenated silicon (a-Si:H) as active semiconductor layer and substoichiometric silicon nitride (SiN) as gate insulator. The work refers to the degradation at room temperature and low positive and negative gate voltage stresses. The electrical parameters: threshold voltage ($V_{th}$), subthreshold swing ($S$) and flat-band voltage ($V_{fb}$) have been determined from the dependence of the drain current on gate voltage ($I_d - V_g$) and the dependence of the capacitance on the gate voltage ($C - V_g$) measurements as function of stress time and bias.\u

Progressive degradation in a-Si: H/SiN thin film transistors

In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region

Current Degradation of a-Si:H/SiN TFTs at Room Temperature and Low Voltages

This paper focuses on the long-term electrical degradation of hydrogenated amorphous silicon (a- Si:H)/silicon nitride (SiN) thin-film transistors (TFTs). Different from the classical method where the electrical degradation of a-Si:H/SiN TFTs is quantified by the shift of the threshold voltage after a period of stress, the authors choose to describe the degradation in terms of drain–current transients that appear during alternative periods of electrical stress. It is shown that the contributions of charge trapping and defect creation to the drain–current degradation can be discriminated based on stress time, stress voltage, and temperature.\ud A numerical model with variable parameters is proposed\ud to fit both short- and long-term transients. This paper shows that the long-term current degradation is related to the changes in the interface trapped charge, whereas the creation of the defects dominates the short-term current degradation.\u