Neuromorphic on-chip recognition of saliva samples of COPD and healthy controls using memristive devices

Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. Results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89% and 86%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD. © 2020, The Author(s)

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9

Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

Producción CientíficaLogic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.European Union’s Horizon 2020 Research and Innovation Programme under Grant 64863

Data retention investigation in Al:HfO 2 -based resistive random access memory arrays by using high-Temperature accelerated tests

In this work, the feasibility of using accelerated tests at high temperatures to assess the data retention on resistive random access memory devices was evaluated on Al: HfO 2-based 1-Transistor-1-resistor 4 kbit arrays. By annealing the samples at four different temperatures (190, 210, 230, and 260 ° C) for 10 h, different distributions of retention failure times were obtained and modeled by using Weibull distributions. Based on the temperature dependency of these distributions, the Arrhenius activation energy of the degradation process was calculated (1.09 eV). In addition, the maximum temperature that guarantees a retention time to failure of a 10 year lifetime was extrapolated (105 ° C)