4,223 research outputs found
Preliminary Investigation of Cyclic De-Icing of an Airfoil Using an External Electric Heater
An investigation was conducted in the NACA Lewis icing research tunnel to determine the characteristics and requirements of cyclic deicing of a 65,2-216 airfoil by use of an external electric heater. The present investigation was limited to an airspeed of 175 miles per hour. Data are presented to show the effects of variations in heat-on and heat-off periods, ambient air temperature, liquid-water content, angle of attack, and. heating distribution on the requirements for cyclic deicing. The external heat flow at various icing and heating conditions is also presented. A continuously heated parting strip at the airfoil leading edge was found necessary for quick, complete, and consistent ice removal. The cyclic power requirements were found to be primarily a function of the datum temperature and heat-on time, with the other operating and meteorological variables having a second-order effect. Short heat-on periods and high power densities resulted in the most efficient ice removal, the minimum energy input, and the minimum runback ice formations. The optimum chordwise heating distribution pattern was found to consist of a uniform distribution of cycled power density in the impingement region. Downstream of the impingement region the power density decreased to the limits of heating which, for the conditions investigated, extended from 5.7 percent chord on the upper surface of the airfoil to 8.9 percent chord on the lower surface. Ice removal did not take place at a heater surface temperature of 32 F; surface temperatures of approximately 50 to 100 F were required to effect removal. Better de-icing performance and greater energy savings would be possible with a heater having a higher thermal efficiency
Design for pre-bond testability in 3D integrated circuits
In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka
Dedication
This issue of the Saint Louis University Law Journal is dedicated to a great man – Judge Theodore McMillian. A product of the City of St. Louis and Saint Louis University School of Law, he has shaped his origins as much as they have shaped him. You will read of his many accomplishments in the pages ahead. You will read of the respect and admiration which he inspires in others. You will read of a human being who is a role model for all who wish to be good, honorable, and principled lawyers, judges, and citizens
A comparison of calculated and measured background noise rates in hard X-ray telescopes at balloon altitude
An actively shielded hard X-ray astronomical telescope has been flown on stratospheric balloons. An attempt is made to compare the measured spectral distribution of the background noise counting rates over the energy loss range 20-300 keV with the contributions estimated from a series of Monte Carlo and other computations. The relative contributions of individual particle interactions are assessed
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