A High Performance DDR3 SDRAM Controller

The paper presents the implementation of compliant DDR3 memory controller. It discusses the overall architecture of the DDR3 controller along with the detailed design and operation of its individual sub blocks, the pipelining implemented in the design to increase the design throughput. It also discusses the advantages of DDR3 memories over DDR2 memories operation. Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market in recent years and are widely used for networking systems. These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost. However, because of the high-speed interface technology and complex instruction-based memory access control, a specific purpose memory controller is necessary for optimizing the memory access trade off. In this paper, a specific purpose DDR3 controller for highperformance is proposed

Ultra low power high speed domino logic circuit by using FinFET technology

Scaling of the MOSFET face greater challenge by extreme power density due to leakage current in ultra deep sub-micron (UDSM) technology. To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper utilize the property of FinFET in domino logic, for high speed operation and reduction of power consumption in wide fan-in OR gate. Proposed circuit is simulated in FinFET technology by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. For 8 and 16 input OR gate we save average power 11.5%,11.39% in SFLD, 22.97%, 18.12% in HSD, 30.90%, 34.57% in CKD in SG mode and for LP mode 11.26%, 15.78% in SFLD, 19.74%, 17.94% in HSD, 45.23%, 34.69% in CKD respectivel

Dielectric Resonator Antenna for X band Microwave Application

ABSTRACT: A simple Dielectric Resonator Antenna (DRA) for X band frequency operation is proposed in this paper. X band is a microwave band lies between frequency range 8 to 12 GHz. In proposed DRA reflector plane is used beneath the microstrip feed line with a small air gap, introduced between feed substrate and reflector plane to reduce the back lobe. Slot coupling is used to excite this DRA. Proposed DRA design gives dual band operation in X band and resonates at frequency 8.6 GHz and 10.3 GHz. Antenna design offers minimum return loss of -20.3 db and -24.5 db at 8.6 GHz and 10.3 GHz respectively. It also offers high front to back ratio (FBR) of 12.35db and 9.83 db at 8.65 GHz and 10.3 GHz respectively. Return loss impedance bandwidth of 390 MHz (4.5%) for Band I and 730MHz (7.3%) for band II is obtained. Simple DRA design with high FBR is proposed here for X band application that shows a total bandwidth of 11.8%. DRA is analysed using Ansoft HFSS based on finite element method. Radiation characteristics of this DRA are observed at resonating frequencies. This DRA is useful at microwave X band application such as satellite communication

A prospective randomized study for comparison of haemodynamic changes and recovery characteristics with propofol and sevoflurane anaesthesia during laparoscopic cholecystectomies

Background: Day care laparoscopic surgical procedures are rapidly increasing nowadays. Rapid emergence and early recovery from anaesthesia with minimal complications are desired. Both propofol and sevoflurane meet above criteria and established as agents of choice in laparoscopic surgeries for induction and maintenance of anaesthesia. So this study aimed to compare sevoflurane with propofol for intraoperative haemodynamic changes with postoperative recovery profile in patient’s undergone laparoscopic cholecystectomies under general anaesthesia.Methods: In this prospective randomized study, sixty patients of either sex, 18-60 years with ASA grade 1 and 2 scheduled for laparoscopic cholecystectomies under general anaesthesia were randomly allocated into two groups. In Group S, patients were maintained on sevoflurane anaesthesia (0.5-2.5%) while in Group P, patients were maintained with propofol infusion (75-125 µg/kg/min) along with O2 (50%) and N2O (50%).The intraoperative haemodynamic parameters, recovery characteristics and postoperative nausea and vomiting (PONV) were observed in both groups.Results: The mean baseline haemodynamic parameters (HR, SBP, DBP, MBP, SpO2 and EtCO2) were comparable in both groups, (P>0.05). No significant difference in HR was at observed any time interval, P>0.05, however, SBP, DBP and MBP were significantly lower in propofol group at different time intervals, P<0.05, but clinically not significant and patients remained haemodynamically stable in both groups. The mean time for all recovery characteristics were significantly shorter in sevoflurane group as compared to propofol group, (P<0.01). However the incidence of PONV was significantly more in sevoflurane group.Conclusions: Sevoflurane can be used as an effective alternative to propofol for maintenance of anaesthesia in day care laparoscopic procedures as it has better recovery profile with stable haemodynamic parameters

Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier

900-904The IEEE-754 standard floating point multiplier that provides highly precise computations to achieve high throughput and low area on the IC have been improved by insertion of pipelining technique. Floating point multiplier-using pipelining has been simulated, analyzed and its superiority over traditional designs is discussed. To achieve pipelining, one must subdivide the input process into sequence subtasks, each of which can be executed by specialized hardware stage that operates concurrently with other stages in the pipeline without the need of extra computing units. Detailed synthesis and simulation report operated upon Xilinx ISE 5.2i and Modelsim software is given. Hardware design is implemented on Virtex FPGA chips

Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder

354-357Many Digital Signal Processing (DSP) algorithms use floating-point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal of every VLSI designer. This paper presents a comparison of pipelined floating-point adder complaint with IEEE 754 format with an unpipelined adder also complaint with IEEE 754 format. It describes the IEEE floating-point standard 754. A pipelined floating point adder based on IEEE 754 format is developed and the design is compared with that of an unpipelined floating point adder and a rigorous analysis is done for speed, area, and power considerations. The functional partitioning of the adder into four distinct stages operates simultaneously for different serial input data stream. It not only increases the speed but also is energy efficient. All these improvements are at the cost of slight increase in the chip area. The basic methodology and approach used for VHDL (Very Large Scale Integration Hardware Descriptive Language) implementation of the floating-point adder are also described. Detailed synthesis report operated upon Xilinx ISE 5.2i software and Modelsim is given. The hardware design is implemented on Spartan IIE FPGA chip

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper