5,991 research outputs found
Improvement on 1/f noise properties of nitrided n-MOSFET's by backsurface argon bombardment
The 1/f noise properties of nitrided n-MOSFET's bombarded by low-energy (550 eV) argon-ion beam are investigated. It is found that after bombardment, 1/f noise, and its degradation under hot-carrier stress are reduced, and both exhibit a turnaround behavior with bombardment time for a given ion energy and intensity. The physical mechanism involved is probably enhanced interface hardness resulting from bombardment-induced stress relief in the vicinity of the oxide/Si interface. Moreover, from the frequency dependence of the noise, it is revealed that the nitrided devices have a nonuniform trap distribution increasing toward the oxide/Si interface which can be modified by the backsurface bombardment.published_or_final_versio
Interface properties of NO-annealed N2O-grown oxynitride
The oxide/Si interface properties of gate dielectric prepared by annealing N2O-grown oxide in an NO ambient are intensively investigated and compared to those of O2-grown oxide with the same annealing conditions. Hot-carrier stressings show that the former has a harder oxide/Si interface and near-interface oxide than the latter. As confirmed by SIMS analysis, this is associated with a higher nitrogen peak concentration near the oxide/Si interface and a larger total nitrogen content in the former, both arising from the initial oxidation in N2O instead of O2.published_or_final_versio
Dynamic-stress-induced enhanced degradation of 1/f noise in n-MOSFET's
AC-stress-induced degradation of 1/f noise is investigated for n-MOSFET's with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under ac stress is far more serious than that under dc stress. For an ac stress of VG = 0 approx. 0.5 VD, generations of both interface state (ΔDit) and neutral electron traps (ΔNet) are responsible for the increase of 1/f noise, with the former being dominant. For another ac stress of VG = 0 approx. VD, a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔNet and generation of another specie of electron traps, plus a small amount of ΔDit. Moreover, under the two types of ac stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation.published_or_final_versio
Electrical properties of different NO-annealed oxynitrides
This journal issues contain proceedings of the 2nd International Conference on Amorphous and Crystalline Insulating Thin Films II ... 1998Performances of gate dielectrics prepared by double-nitridation in NO and N2O are investigated. Stronger oxide/Si interface bonding, less charge trapping and larger charge-to-breakdown are observed for such gate dielectrics than singly NO-nitrided gate dielectric. The physical mechanisms behind the findings are attributed to larger nitrogen peak concentration located almost at the oxide/Si interface and total nitrogen content near the oxide/Si interface of these gate dielectrics.postprin
1/f noise in n-channel metal-oxide-semiconductor field-effect transistors under different hot-carrier stresses
Degradation mechanisms contributing to increased 1/f noise of n-channel metaloxide-semiconductor field-effect transistors (n-MOSFETs) after different hot-carrier stresses are investigated. It is demonstrated that for any hot-carrier stress, the stress-induced enhancement of 1/f noise is mainly attributed to increased carrier-number fluctuation arising from created oxide traps, while enhanced surface-mobility fluctuation associated with electron trapping at preexisting and generated fast interface states and near-interface oxide traps is also responsible under maximum substrate- and gate-current stresses. Besides thermal-oxide n-MOSFETs, nitrided-oxide devices are also used to further support the above analysis. © 1999 American Institute of Physics.published_or_final_versio
Effects of wet N 2O oxidation on interface properties of 6H-SiC MOS capacitors
Oxynitrides were grown on n- and p-type 6H-SiC by wet N 2O oxidation (bubbling N 2O gas through deionized water at 95°C) or dry N 2O oxidation followed by wet N 2O oxidation. Their oxide/SiC interfaces were investigated for fresh and stressed devices. It was found that both processes improve p-SiC/oxide but deteriorate n-SiC/oxide interface properties when compared to dry N 2O oxidation alone. The involved mechanism could be enhanced removal of unwanted carbon compounds near the interface due to the wet ambient, and hence a reduction of donor-like interface states for the p-type devices. As for the n-type devices, incorporation of hydrogen-related species near the interface under the wet ambient increase acceptor-like interface states. In summary, the wet N 2O oxidation can be used for providing comparable reliability for n- and p-SiC MOS devices, and especially obtaining high-quality oxide-SiC interface in p-type MOS devices.published_or_final_versio
A comparison between NO-annealed O2- and N2O-grown gate dielectrics
Qualities of oxynitrides prepared by annealing O2- and N2O-grown oxides in NO ambient are investigated. Harder oxide/Si interface, less charge trapping and higher charge-to-breakdown characteristics are observed in NO-annealed N2O-grown (N2ONO) oxynitride than NO-annealed O2-grown (O2NO) oxynitride. The involved mechanism lies in higher interfacial nitrogen concentration and total nitrogen content in N2ONO oxynitride than O2NO oxynitride for the same anneal temperature and time.published_or_final_versio
A study on interface and charge trapping properties of nitrided n-channel metal-oxide-semiconductor field-effect transistors by backsurface argon bombardment
A low-energy (550 eV) argon-ion beam was used to directly bombard the backsurface of nitrided n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) after the completion of all conventional processing steps. The interface and oxide-charge trapping characteristics of the bombarded MOSFETs were investigated as compared to nonbombarded and reoxidized-nitrided n-MOSFETs. It was found that after bombardment, interface state density decreases and interface hardness against hot-carrier bombardment enhances, and oxide charge trapping properties were also improved. The improvements exhibit a turnaround behavior depending on bombardment conditions and could be attributed to stress compensation in the vicinity of the Si/SiO2 interface and an annealing effect. © 1997 American Institute of Physics.published_or_final_versio
Effects of annealing gas species on the electrical properties and reliability of Ge MOS capacitors with high-k Y 2O 3 gate dielectric
In this work, Ge MOS capacitors with Y 2O 3 gate dielectric were fabricated. The effects of annealing in N 2, NH 3 O 2 or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y 2O 3 dielectric. On the other hand, the NH 3 annealing resulted in H-related traps while the O 2 annealing suffered from extra GeO x growth, thus both degrading the performance of the devices. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2009), Xi'an, China, 25-27 December 2009.
In Proceedings of EDSSC, 2009, p. 243-24
Fabrication and electrical characterization of MONOS memory with novel high-κ gate stack
A novel high-κ gate stack structure with HfON/SiO 2 as dual tunneling layer (DTL), AIN as charge storage layer (CSL) and HfAIO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si 3N 4/SiO 2 as DTL, HfO 2 as CSL and Al 2O 3 as BL. Results show a large memory window of 3.55 V at PIE voltage of +8 V/-I5 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAIO/AIN/(HfON/SiO 2)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-κ HfON/SiO 2 DTL, high trapping efficiency of the high-κ AIN material and effective blocking role of the high-κ HfAIO BL. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-52
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