Sensor Grid Design For High Resolution 3D Acoustic Measurements Of Musical Instruments.

Much of the research undertaken in the field of musical acoustic analysis involves (electro)mechanical actuation of the instruments under measurement conditions without the musician present. This has the benefit of repeatability, so that apparatus can be designed in order to make asynchronous measurements at different points in 3D space. It also means that the instrument is analysed in its pure form without any acoustic aberrations presented by a human performer. However it has been found that when a musician performs on the instrument, this repeatability is absent (despite the musician’s self-belief in their own consistency) and an alternative approach must be taken to make 3-dimensional acoustic measurements with the musician present. Musicians could of course be present during actuated musical instrument analysis but this is not (yet) a common approach. The research project described in this paper is ongoing and recent developments of sensor grid geometry are presented here along with some promising initial results. The sensor array geometry has been investigated with respect to: optimal spacing, minimising errors in data interpolation at high frequency, and practicality for construction and actual use. Some preliminary data from a section of the array grid has been obtained and is presented here in order to demonstrate the robustness of the data at high frequencies. There is some discussion of the likely errors in interpolation of the data and some further ideas are explored regarding the manipulation of the recorded data

CMRR-Bandwidth Extension Technique for CMOS Differential Amplifiers

An exemplary design demonstrates how to extend the common-mode rejection ratio (CMRR) bandwidth of a CMOS differential amplifier. The design presented uses MOSFETs with a channel length of 180nm. A novel circuit technique is employed that partially compensates for the output capacitance of the tail current sink, thereby more than quadrupling the CMRR bandwidth in the example considered

Minimal Power Start-Up Circuit Design for Self-Biased CMOS Current Generators

A new start-up circuit configuration, with minimal standby power dissipation, is proposed for CMOS self-biased current generators. Using standard 0.13µm CMOS technology, simulation results show that for a supply voltage range 1.8V to 2.5V, and a temperature range −40ºC to +85ºC, the circuit standby power dissipation is less than 20nW

Theoretical Study of the Circuit Architecture of the Basic CFOA and Testing Techniques

This paper examines the closed-loop characteristics of the basic CFOA, and in particular, the dynamic response. Additionally, it also examines the design and advantages of the CFOA regarding its ability to provide a significantly constant closed-loop bandwidth for closed-loop voltage gain. Secondly, the almost limitless slew–rate provided by the class AB input stage that makes it superior to the VOA counterpart. Additionally; this paper also concerns the definitions and measurements of the terminal parameters of the CFOA, regarded as a ‘black box’. It does not deal with the way that these parameters are related to the properties of the active passive and active components of a particular circuit configuration. Simulation is used in terminal parameter determination: this brings with it the facility of using test conditions that would not normally prevail in a laboratory test on silicon implementations of the CFOAs. Thus, we can apply 1mA and 1mV test signals from, respectively, infinite and zero source impedances that range in frequency from d.c to some tens of GHz. Also, we assume the existence of resistors with identical Ohmic value and very high value ideal capacitors. Where appropriate, practical test methods are referred to physical laboratory prototypes

Technique for increasing the output impedance of CMOS regulated cascode circuits

A technique is proposed for the design of a modified CMOS regulated cascode having an output impedance significantly greater than that of a conventional regulated cascode. Simulation results for an illustrative design, operating at 10µA from a 1V supply, show an increase in output resistance from 636MΩ and output bandwidth of 55kHz for a conventional circuit to 6.68GΩ and 389kHz, respectively, for the proposed design

Improved designs for current feedback op-amps

The performance of the current feedback op-amps (CFOAs) is very much determined by the input stage of CFOAs, including common-mode rejection ratio (CMRR). Two new CFOAs topologies are presented in this article: one topology uses a cascoding technique, and the second one uses a bootstrapping technique, both of which provide a much better CMRR and lower DC offset voltage than the conventional CFOAs. Moreover, the new CFOAs design exhibits an extended high frequency bandwidth, with a gain accuracy improvement. Applications requiring constant bandwidth with variable (closed loop) gain will benefit from the proposed topologies

An investigation on the discrete-time nature of excess phase and jitter

Excess phase in oscillators or phase locked loops is a very important design specification typically modelled as a continuous time signal. In this paper we explain why, when the quantity of interest is jitter, excess phase should be treated as a discrete quantity. This treatment helps explaining noise folding in frequency dividers and analyse its consequences in Phase Locked Loops

A novel current reference in 45nm cmos technology

In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/0C against temperature variation of -400C –1200C and line sensitivity of 337ppm/V against supply variation of 0.6–1.8V, while consuming 135uW from 1.8V supply and occupying 5184um

A novel current-feedback op-amp exploiting bootstrapping techniques

The operation of the conventional current feedback operational amplifier (CFOA) is reviewed and its performance parameters used as benchmarks in the development of a new input stage architecture that provides a common-mode rejection ratio (CMRR) improvement of some 45 dB and offset voltage less than 10 mV

A Microwatt low voltage bandgap reference for bio-medical applications

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area