Degradation of x-Si:H TFTs caused by Electrostatic Discharge

This paper gives results of experimental analysis of impact of electrostatic discharge (ESD) pulse on amorphous silicon thin film transistors (-Si:H TFT). The development of degradation of the electron mobility and the threshold voltage is presented. Failure analysis has been done and two failure mechanisms have been identifie

Electrostatic discharge effects in thin film transistors

Although amorphous silicon thin film transistors (α-Si:H TFT’s) have a very low electron mobility and pronounced instabilities of their electrical characteristics, they are still very useful and they have found their place in the semiconductors industry, as they possess some very good properties: they can be deposited under low temperature and over a large area, and they are very cheap. It is proved from practice that electrostatic discharge (ESD) is one of the most important issues in thin film electronics. It jeopardizes reliable operation of thin film transistors, firstly during the manufacturing process in the cleanroom, and also in some cases during their operation. Having a large on-resistance, α-Si:H TFT’s are very difficult from the point of ESD protection, as it is difficult to sink the current. Another difficulty for the ESD protection is that they are also built on an insulation substrate. Finally, the testing methods and the design rules that are already developed for the silicon integrated circuits are not applicable on the amorphous silicon TFT’s. Therefore an original design has to be created in order to protect TFT circuits from the electrostatic discharge

Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations

Analysis of the electrical breakdown in hydrogenated amorphous silicon thin-film transistors

Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to