KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs

In a modern FPGA system-on-chip design, it is often insufficient to simply assess the total power consumption of the entire circuit by design-time estimation or runtime power rail measurement. Instead, to make better runtime decisions, it is desirable to understand the power consumed by each individual module in the system. In this work, we combine boardlevel power measurements with register-level activity counting to build an online model that produces a breakdown of power consumption within the design. Online model refinement avoids the need for a time-consuming characterisation stage and also allows the model to track long-term changes to operating conditions. Our flow is named KAPow, a (loose) acronym for ‘K’ounting Activity for Power estimation, which we show to be accurate, with per-module power estimates as close to ±5mW of true measurements, and to have low overheads. We also demonstrate an application example in which a permodule power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by over 8%

Boundary element methods in the prediction of the acoustic damping of ship whipping vibrations

Damping of ship whipping vibrations following a slam due to wave impact is traditionally assumed to be primarily of material or structural origin. However, several mechanisms of energy dissipation to the surrounding water exist, including gravity and acoustic waves. Neither transports much energy for the lowest frequency modes, in which the acoustic wavelength may be an order or magnitude greater than the ship length whereas the gravity wavelength is at least an order of magnitude shorter than the ship beam. However, the acoustic damping ratio increases as the fourth power of frequency, becoming significant for higher frequency modes

Slam excitation scales for a large wave piercing catamaran and the effect on structural response

A unique slamming process is observed on high speed wave piercing catamarans (WPCs) such as those manufactured by INCAT Tasmania (shown in Fig. 1). For conventional catamarans, wet-deck slamming constitutes a significant design load and is managed through proper design of the tunnel height for the proposed operating conditions. While methods have been developed for prediction of wet-deck slam occurrence and slam magnitude in conventional catamarans (for example Ge et al., 2005) the significant differences in geometry limit application to wave piercing catamarans. Although slamming of wave piercing catamarans may be categorised as a wet-deck slam, the INCAT Tasmania wave piercing catamarans include a forward centre bow to prevent deck diving which significantly alters the water entry and slamming characteristics

architect: Arbitrary-precision Constant-hardware Iterative Compute

Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed or floating point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the algorithm for enough iterations or because the arithmetic in some iterations was insufficiently precise? There is no easy way to answer this question, so users will often over-budget precision in the hope that the answer will always be to run for a few more iterations. We propose a fundamentally new approach: armed with the appropriate arithmetic able to generate results from most-significant digit first, we show that fixed compute-area hardware can be used to calculate an arbitrary number of algorithmic iterations to arbitrary precision, with both precision and iteration index increasing in lockstep. Thus, datapaths constructed following our principles demonstrate efficiency over their traditional arithmetic equivalents where the latter’s precisions are either under- or over-budgeted for the computation of a result to a particular accuracy. For the execution of 100 iterations of the Jacobi method, we obtain a 1.60x increase in frequency and 15.7x LUT and 50.2x flip-flop reductions over a 2048-bit parallel-in, serial-out traditional arithmetic equivalent, along with 46.2x LUT and 83.3x flip-flop decreases versus the state-of-the-art online arithmetic implementation

The influence of the centre bow and wet-deck geometry on motions of wave piercing catamarans

The effects of tunnel height and centre bow length on the motions of a 112-m wave-piercer catamaran with an above-water centre bow were investigated through model tests. Five alternative centre bow configurations were considered, and multiple series of model tests were conducted in regular head sea waves. The results showed that both heave and pitch increased over a wide range of wave encounter frequency as the wet-deck height of the catamaran model increased. However, increasing the length of the centre bow showed an increase in the pitch but a decrease in the heave for a limited range of wave encounter frequency near the heave and pitch resonance frequencies of the catamaran model. The positions of minimum vertical displacement were found to be aft of the longitudinal centre of gravity, between 20% and 38% of the overall length from the transom. Increase in the wet-deck height and consequently the archway clearance between the main hulls and centre bow also resulted in an increase in the vertical displacement relative to the undisturbed water surface in the centre bow area. The results also indicated the vulnerability to wet-deck slamming for the different bow and wet-deck designs

KAPow: high-accuracy, low-overhead online per-module power estimation for FPGA designs

In an FPGA system-on-chip design, it is often insufficient to merely assess the power consumption of the entire circuit by compile-time estimation or runtime power measurement. Instead, to make better decisions, one must understand the power consumed by each module in the system. In this work, we combine measurements of register-level switching activity and system-level power to build an adaptive online model that produces live breakdowns of power consumption within the design. Online model refinement avoids time-consuming characterisation while also allowing the model to track long-term operating condition changes. Central to our method is an automated flow that selects signals predicted to be indicative of high power consumption, instrumenting them for monitoring. We named this technique KAPow, for 'K'ounting Activity for Power estimation, which we show to be accurate and to have low overheads across a range of representative benchmarks. We also propose a strategy allowing for the identification and subsequent elimination of counters found to be of low significance at runtime, reducing algorithmic complexity without sacrificing significant accuracy. Finally, we demonstrate an application example in which a module-level power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by up to 7%