Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology

The development of new integrated high-speed Si receivers is requested for short distance optical data link and emerging optical storage (OS) systems, notably for the Gb/s Ethernet standard [1] - [8] and Blue DVD (Blu-Ray, HDDVD) [3], [4], [9]. As requirements on bandwidth, gain, power consumption as well as low read-out noise and cost are quite severe, an optimal design strategy of a monolithically integrated solution, i.e. with on-chip photodetector and transimpedance amplifier (TIA), is required. In optical communication, however, non integrated detectors are usually employed [2] - [8] since the particular indirect energy band properties of Silicon make this semiconductor not very efficient for optical reception at 850nm wavelength. As Si is the most widely used and low cost semiconductor material in electronics and due to the availability of low-cost 850nm transmitters, there is yet a great interest and challenge to integrate such receivers. 1 to 10 Gb/s, high sensitivity and low complexity, low-cost silicon photodetectors for the monolithic integration of optical receivers for short distance applications at 850nm are really an issue as the Si absorption thickness required for high-speed (low transit time and low capacitance) favors thin-film technologies for which the responsivity is low. Some solutions exist but at the price of more costly and complex fabrication processes [10-16]. At the system level, owing to its low dark current (pA range) [17], low capacitor (10fF) for the photodetector [1] and possibility to integrate this detector with high-performance low-capacitance transistors, global thin-film SOI monolithically integrated photoreceivers have potentially higher gain and lower noise performances which in turn, as we will show here, can increase the C-sensitivity and alleviate this requirement on the photodetector itself. Furthermore only SOI photodiodes have so far achieved bandwidth compatible with the 10Gb/s specification and even higher data rate among the "easy to integrate" Si photodetectors [1], [15], [16] and [18]. In the blue and UV wavelengths, these diodes achieve a high responsivity [17] and then combine all the advantages of high speed, low dark current and finally high sensitivity [1]. This makes SOI receivers the best candidate for blue DVD applications and future optical storage generation. This also suggests that blue wavelength for multi Gb/s short reach optical communication could be used in a near future under the condition that the recent progresses in blue emitting sources make them available [17, 19]. We present here a top-down design methodology, fully validated by Eldo circuit simulations [20] and experimental measurements, which allows to predict and optimize, starting from the speed requirements and the technological parameters, the architecture and performances of the receiver. Our approach generalizes the one proposed in [21] to all inversion regimes. In addition our design strategy is based on the gm id methodology [22] and allows one to optimize the diode and the transimpedance in a simultaneous way. Thanks to this modeling and the low capacitance of thin-film integrated SOI photodiodes, we have optimized various monolithic optical front-end suitable for 1 to 10 Gb/s short distance communication or Blue DVD applications that show the potentials of 0.13μm Partially-Depleted (PD) SOI CMOS implementation in terms of gain, sensitivity, power consumption, area and noise. In section 2 (Optical Receivers Basics), the simple resistor system is first presented as well as its limitations. The transimpedance amplifier is then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability are derived. Important parameters to compare transimpedance amplifiers are also discussed as well as architectures most often used in the high speed communication area. Then in section "Design of Multistage Transimpedance Amplifiers", we present our top-down methodology to design transimpedance amplifiers in the case where the voltage gain of the voltage amplifier used in the TIA is independent of the feedback resistor Rf. This is usually the case when the TIA bandwidth is not too close to the transistors frequency limit ft of a given technology and leads to a multi-stage approach. Our design procedure is then applied to the design of a 3 stages 1GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology. Finally, in section "Single stage Transimpedance Amplifier Modeling", we present a top-down methodology to design transimpedance amplifiers when the voltage gain depends on Rf. This is the case for very high-speed singlestage transimpedance amplifiers. Our design procedure is then applied to the design of a single stage 10GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology and to the design of a 1GHz bandwidth single stage TIA in a 0.5 μm FD-SOI CMOS technology

Analysis and design of a family of low-power class AB operational amplifiers

PostprintA new class AB output stage is presented which extends a family of recently proposed stages based on current mirrors without requiring extra-compensation capacitances. In-depth circuit analysis also shows the significant advantage of such stages for low-power consumption and leads to the derivation of an optimum design strategy. Experimental realizations are described, in particular a micropower amplifier for cardiac pacemaker application

A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator

PostprintThe design of a sensing channel for implantable cardiac pacemakers in CMOS on silicon-on-insulator (SOI) technology is presented. The total current consumption is lowered to only 110nA thanks to the optimization at the architectural level, the application of a new class AB design approach at the operational transconductance amplifier (OTA) and the exploitation of the improved characteristics of thin-film fully depleted SOI CMOS technology. The core of the prototyped sense channel (OTA and comparator) occupies 0.06mm/sup 2/ in a 3/spl mu/m technology and is suitable for operation from implantable grade batteries with power supply voltages from 2.8V down to 2V. Experimental results of the building blocks and complete sensing channel performance are presented. The achieved results demonstrate the benefits of fully depleted SOI CMOS technology for micropower applications

Detection mechanism in highly sensitive ZnO nanowires network gas sensors

Metal-oxide nanowires are showing a great interest in the domain of gas sensing due to their large response even at a low temperature, enabling low-power gas sensors. However their response is still not fully understood, and mainly restricted to the linear response regime, which limits the design of appropriate sensors for specific applications. Here we analyse the non-linear response of a sensor based on ZnO nanowires network, both as a function of the device geometry and as a response to oxygen exposure. Using an appropriate model, we disentangle the contribution of the nanowire resistance and of the junctions between nanowires in the network. The applied model shows a very good consistency with the experimental data, allowing us to demonstrate that the response to oxygen at room temperature is dominated by the barrier potential at low bias voltage, and that the nanowire resistance starts to play a role at higher bias voltage. This analysis allows us to find the appropriate device geometry and working point in order to optimize the sensitivity. Such analysis is important for providing design rules, not only for sensing devices, but also for applications in electronics and opto-electronics using nanostructures networks with different materials and geometries

Low temperature tunneling current enhancement in silicide/Si Schottky contacts with nanoscale barrier width

The low temperature electrical behavior of adjacent silicide/Si Schottky contacts with or without dopant segregation is investigated. The electrical characteristics are very well modeled by thermionic-field emission for non-segregated contacts separated by micrometer-sized gaps. Still, an excess of current occurs at low temperature for short contact separations or dopant-segregated contacts when the voltage applied to the device is sufficiently high. From two-dimensional self-consistent non-equilibrium Green's function simulations, the dependence of the Schottky barrier profile on the applied voltage, unaccounted for in usual thermionic-field emission models, is found to be the source of this deviation

MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design

PostprintTrabajo presentado en ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions

Band gap reduction in highly-strained silicon beams predicted by first-principles theory and validated using photoluminescence spectroscopy

A theoretical study of the band gap reduction under tensile stress is performed and validated through experimental measurements. First-principles calculations based on density functional theory (DFT) are performed for uniaxial stress applied in the [001], [110] and [111] directions. The calculated band gap reductions are equal to 126, 240 and 100 meV at 2$\%$ strain, respectively. Photoluminescence spectroscopy experiments are performed by deformation applied in the [110] direction. Microfabricated specimens have been deformed using an on-chip tensile technique up to ~1$\%$ as confirmed by back-scattering Raman spectroscopy. A fitting correction based on the band gap fluctuation model has been used to eliminate the specimen interference signal and retrieve reliable values. Very good agreement is observed between first-principles theory and experimental results with a band gap reduction of, respectively, 93 and 91 meV when the silicon beam is deformed by 0.95$\%$ along the [110] direction

Low-Wavelengths SOI CMOS Photosensors for Biomedical Applications

INTRODUCTION : Biological agents may be characterized (in terms of quantity (or concentration), purity, nature) using optical ways like spectrometry, fluorometry and real-time PCR for example. Most of these techniques are based on absorbance or fluorescence. Indeed, many biological molecules can absorb the light when excited at wavelengths close to blue and ultraviolet (UV). For example, DNA, RNA and proteins feature an absorption peak in the deep UV, more precisely around 260 and 280 nm (Karczemska & Sokolowska, 2001). This work is widely focused on those wavelengths. A biological sample concentration measurement method can be based on UV light absorbance or transmittance, as already known and realized with high-cost and large-size biomedical apparatus. But, often, the difficulties come from the limitation for measuring very small concentrations (close to a few ng/µL or lower) since the measurement of such small light intensity variations at those low wavelengths requires a precise light source, and very efficient photodetectors. Reducing the dimensions of such a characterization system further requires a small light source, a miniaturized photosensor and a processing system with high precision to reduce the measurement variations. Some light-emitting diodes (LED) performing at those UV wavelengths have recently appeared and may be used to implement the light source. Concerning the optical sensor, while accurate but high-cost photosensors in technologies such as AlGaN and SiC provide high sensitivities in UV low wavelengths thanks to their semiconductor bandgap (Yotter & Wilson, 2003), the silicon-on-insulator (SOI) layers absorb the photons in that specific range thanks to an appropriate thickness of the silicon. Adding excellent performances of low power consumption, good temperature behavior and high speed (Flandre et al., 1999; 2001), the SOI technology allows the designers for integrating a specific signal processing integrated CMOS circuit to transform the photocurrent into a digital signal for example. This opens the possibility to build a low-cost, complete and portable microsystem, including the light source, the photodetector and a recipient for the sample to characterize […