Design of ultra low power analog-to-digital converter for ambulatory EEG recording

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 65-67).Portable acquisition of biopotential signals requires the design of compact, energy efficient circuits and systems. Such systems typically include analog-to-digital converter for digitizing signals from AFE and feeding it to DBE. An Ultra low power ADC is designed in this work to be integrated within scalable EEG SoC. The full system can capture EEG signals through 1 up to 8 parallel differential channels that are time division multiplexed into a single ADC. The ADC has a fixed resolution of 10 bits which is sufficient for extraction of bio-markers for seizure detection. A SAR ADC architecture is chosen for this design as it is highly energy efficient for medium to high resolution applications with low speed requirements. A differential capacitive DAC is utilized to enhance the CMRR. Concepts of split-capacitor array and sub-DAC are combined to reduce the DAC area and power consumption. Charge pumps are used to boost the control voltage of sampling switches. The ADC performs a conversion every 16 clock cycle while being governed by a self-resetting SAR logic. The sampling rate can be scaled up to 32 kHz by varying the clock frequency to accommodate different number of channels used. The ADC was designed and fabricated in a 0.18 pm CMOS technology. The entire ADC core consumes 1 pW from 1 V supply at a sampling rate of 32 kHz. The ADC has a maximum DNL and INL of 0.55 LSB and 0.75 LSB respectively. The SNDR and SFDR of the converter are measured at a sampling rate of 32 kHz and 15.5 kHz input tone to be 57.9 dB and 68.5 dBFS respectively. The ADC FOM is 51 fJ/Conv-Step.by Dina Reda El-Damak.S.M

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection

Prolonged energy harvesting for ingestible devices

Ingestible electronics have revolutionized the standard of care for a variety of health conditions. Extending the capacity and safety of these devices, and reducing the costs of powering them, could enable broad deployment of prolonged-monitoring systems for patients. Although previous biocompatible power-harvesting systems for in vivo use have demonstrated short (minute-long) bursts of power from the stomach, little is known about the potential for powering electronics in the longer term and throughout the gastrointestinal tract. Here, we report the design and operation of an energy-harvesting galvanic cell for continuous in vivo temperature sensing and wireless communication. The device delivered an average power of 0.23 μW mm⁻² of electrode area for an average of 6.1 days of temperature measurements in the gastrointestinal tract of pigs. This power-harvesting cell could provide power to the next generation of ingestible electronic devices for prolonged periods of time inside the gastrointestinal tract.National Institutes of Health (U.S.) (Grant EB-000244

Prolonged energy harvesting for ingestible devices

Ingestible electronics have revolutionized the standard of care for a variety of health conditions. Extending the capacity and safety of these devices, and reducing the costs of powering them, could enable broad deployment of prolonged monitoring systems for patients. Although prior biocompatible power harvesting systems for in vivo use have demonstrated short minute-long bursts of power from the stomach, not much is known about the capacity to power electronics in the longer term and throughout the gastrointestinal tract. Here, we report the design and operation of an energy-harvesting galvanic cell for continuous in vivo temperature sensing and wireless communication. The device delivered an average power of 0.23 μW per mm2 of electrode area for an average of 6.1 days of temperature measurements in the gastrointestinal tract of pigs. This power-harvesting cell has the capacity to provide power for prolonged periods of time to the next generation of ingestible electronic devices located in the gastrointestinal tract

Power management circuits for ultra-low power systems

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.Includes bibliographical references (pages 137-145).Power management circuits perform a wide range of vital tasks for electronic systems including DC-DC conversion, energy harvesting, battery charging and protection as well as dynamic voltage scaling. The impact of the efficiency of the power management circuits is highly profound for ultra-low power systems such as implantable, ingestible or wearable devices. Typically the size of the system for such applications does not allow the integration of a large energy storage device. Therefore, extreme energy efficiency of the power management circuits is critical for extended operation time. In addition, flexibility and small form factor are desirable to conform to the human body and reduce the system's over all size. Thus, this thesis presents highly efficient and miniature power converters for multiple applications using architecture and circuit level optimization as well as emerging technologies. The first part presents a power management IC (PMIC) featuring an integrated reconfigurable switched capacitor DC-DC converter using on-chip ferroelectric caps in 130 nm CMOS process. Digital pulse frequency modulation and gain selection circuits allow for efficient output voltage regulation. The converter utilizes four gain settings (1, 2/3, 1/2, 1/3) to support an output voltage of 0.4 V to 1.1 V from 1.5 V input while delivering load current of 20 [mu]A to 1 mA. The PMIC occupies 0.366 mm² and achieves a peak efficiency of 93% including the control circuit overhead at a load current of 500 [mu]A. The second part presents a solar energy harvesting system with 3.2 nW overall quiescent power. The chip integrates self-startup, battery management, supplies 1 V regulated rail with a single inductor and supports power range of 10 nW to 1 [mu]W. The control circuit is designed in an asynchronous fashion that scales the effective switching frequency of the converter with the level of the power transferred. The ontime of the converter switches adapts dynamically to the input and output voltages for peak-current control and zero-current switching. The system has been implemented in 180 nm CMOS process. For input power of 500 nW, the proposed system achieves an efficiency of 82%, including the control circuit overhead, while charging a battery at 3 V from 0.5 V input. The third part focuses on developing an energy harvesting system for an ingestible device using gastric acid. An integrated switched capacitor DC-DC converter is designed to efficiently power sensors and RF transmitter with a 2.5 V regulated voltage rail. A reconfigurable Dickson topology with four gain settings (3, 4, 6, 10) is used to support a wide input voltage range from 0.3 V to 1.1 V. The converter is designed in 65 nm CMOS process and achieves a peak efficiency of 80% in simulation for output power of 2 [mu]W. The last part focuses on flexible circuit design using Molybdenum Disulfide (MoS₂), one of the emerging 2D materials. A computer-aided design flow is developed for MoS₂-based circuits supporting device modeling, circuit simulation and parametric cell-based layout - which paves the road for the realization of large-scale flexible MoS₂ systems.by Dina Reda El-Damak.Ph. D

Image Encryption Based on Fourier-DNA Coding for Hyperchaotic Chen System, Chen-Based Binary Quantization S-Box, and Variable-Base Modulo Operation

This research work extends the hyperchaotic 4D Chen system into the fractional-order domain to carry out image encryption over 3 stages. For the first encryption stage, the discrete Fourier transform (DFT) of the numerical solution of the fractional-order Chen system is obtained, quantized, and employed in carrying out DNA coding. For the second stage, a robust S-box is constructed from the DFT-quantized solution of the Chen system and applied. For the third stage, a Mersenne Twister encryption key is converted to base- $\phi$ , and a modulo operation is applied. The proposed technique is shown to be efficient, secure, and robust, performing comparably to its counterparts in the literature. Average computed values include an MSE of 9610, a PSNR of 8.33 dB, an MAE of 80.22, an information entropy of 7.999, correlation coefficients of zero, an NPCR of $99.62\%$ , and a UACI of $31.46\%$ . It also passes all the NIST SP 800 suite of tests. The main advantages of the proposed technique are its superior key space of 21754 and encryption rate of 72.6 Mbps

A 25 mV-startup cold start system with on-chip magnetics for thermal energy harvesting

Thermal energy harvesting systems use boost converters for high-efficiency low voltage operation, but lack the ability for low voltage startup without off-chip transformers. We present a cold start system that uses integrated magnetics instead of external transformers in a Meissner Oscillator to start up from ultra low voltages, with a switched capacitor DC-DC circuit for additional voltage gain. The oscillator analysis with on-chip magnetics allows device co-optimization for low voltage operation, despite 1000x lower inductance values than off-chip transformers. Co-optimized on-chip transformer and depletion-mode NMOS start up from 25 mV driven directly by a sourcemeter, or 50 mV with a 4.7 Ω series resistance, for the lowest integrated electrical startup. The co-packaged system provides proof of concept for integration with boost converter circuits on a single die to have a fully-integrated low voltage startup solution for thermal energy harvesting applications, without using off-chip transformers

Measurements of electrical energy harvesting from Cu-Zn cell for ingestible devices

<div>Supporting materials for our paper:  "Prolonged energy harvesting for ingestible devices"  Nature Biomedical Engineering, Feb 2017</div><div><br></div><div>Here we present: (1) data collected during our wireless capsule experiments in pigs, (2) the schematics of the board designs used to acquire the data, and (3) the micro controller code that ran the experiments.</div><div><br></div><div>Please see the paper for a full discussion on the methodology, techniques, and interpretation.  Link to the paper: http://dx.doi.org/10.1038/s41551-016-0022</div

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS₂ Circuits with E‑Mode FETs for Large-Area Electronics

Two-dimensional electronics based on single-layer (SL) MoS₂ offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS₂ circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS₂ FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc–dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials