Plasmodium falciparum malaria co-infection with tick-borne relapsing fever in Dakar

Abstract Background West African tick-borne relapsing fever (TBRF) due to Borrelia crocidurae and malaria are co-endemics in Senegal. Although expected to be high, co-infections are rarely reported. A case of falciparum malaria and B. crocidurae co-infection in a patient from Velingara (South of Senegal) is discussed. Case A 28\ua0year-old-male patient presented to Aristide Le Dantec Hospital for recurrent fever. He initially presented to a local post health of Pikine (sub-urban of Dakar) and was diagnosed for malaria on the basis of positive malaria rapid diagnostic test (RDT) specific to Plamodium falciparum . The patient was treated as uncomplicated falciparum malaria. Four days after admission the patient was referred to Le Dantec Hospital. He presented with fever (39\ua0\ub0C), soreness, headache and vomiting. The blood pressure was 120/80\ua0mmHg. The rest of the examination was normal. A thick film from peripheral blood was performed and addressed to the parasitology laboratory of the hospital. Thick film was stained with 10% Giemsa. Trophozoite of P. falciparum was identified at parasite density of 47 parasites per microlitre. The presence of Borrelia was also observed, concluding to malaria co-infection with borreliosis. Conclusions Signs of malaria can overlap with signs of borreliosis leading to the misdiagnosis of the latter. Thick and thin smear or QBC test or molecular method may be helpful to detect both Plamodium species and Borrelia . In addition, there is a real need to consider co-infections with other endemics pathogens when diagnosing malaria

Evaluation of the multiplex real time PCR DermaGenius assay for the detection of dermatophytes in hair samples from Senegal

peer reviewe

The evolving SARS-CoV-2 epidemic in Africa: Insights from rapidly expanding genomic surveillance

INTRODUCTION Investment in Africa over the past year with regard to severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) sequencing has led to a massive increase in the number of sequences, which, to date, exceeds 100,000 sequences generated to track the pandemic on the continent. These sequences have profoundly affected how public health officials in Africa have navigated the COVID-19 pandemic. RATIONALE We demonstrate how the first 100,000 SARS-CoV-2 sequences from Africa have helped monitor the epidemic on the continent, how genomic surveillance expanded over the course of the pandemic, and how we adapted our sequencing methods to deal with an evolving virus. Finally, we also examine how viral lineages have spread across the continent in a phylogeographic framework to gain insights into the underlying temporal and spatial transmission dynamics for several variants of concern (VOCs). RESULTS Our results indicate that the number of countries in Africa that can sequence the virus within their own borders is growing and that this is coupled with a shorter turnaround time from the time of sampling to sequence submission. Ongoing evolution necessitated the continual updating of primer sets, and, as a result, eight primer sets were designed in tandem with viral evolution and used to ensure effective sequencing of the virus. The pandemic unfolded through multiple waves of infection that were each driven by distinct genetic lineages, with B.1-like ancestral strains associated with the first pandemic wave of infections in 2020. Successive waves on the continent were fueled by different VOCs, with Alpha and Beta cocirculating in distinct spatial patterns during the second wave and Delta and Omicron affecting the whole continent during the third and fourth waves, respectively. Phylogeographic reconstruction points toward distinct differences in viral importation and exportation patterns associated with the Alpha, Beta, Delta, and Omicron variants and subvariants, when considering both Africa versus the rest of the world and viral dissemination within the continent. Our epidemiological and phylogenetic inferences therefore underscore the heterogeneous nature of the pandemic on the continent and highlight key insights and challenges, for instance, recognizing the limitations of low testing proportions. We also highlight the early warning capacity that genomic surveillance in Africa has had for the rest of the world with the detection of new lineages and variants, the most recent being the characterization of various Omicron subvariants. CONCLUSION Sustained investment for diagnostics and genomic surveillance in Africa is needed as the virus continues to evolve. This is important not only to help combat SARS-CoV-2 on the continent but also because it can be used as a platform to help address the many emerging and reemerging infectious disease threats in Africa. In particular, capacity building for local sequencing within countries or within the continent should be prioritized because this is generally associated with shorter turnaround times, providing the most benefit to local public health authorities tasked with pandemic response and mitigation and allowing for the fastest reaction to localized outbreaks. These investments are crucial for pandemic preparedness and response and will serve the health of the continent well into the 21st century

Caractérisation et modélisation de nouvelles capacités «Through Silicon Capacitors» à forte intégration pour la réduction de consommation et la montée en fréquence dans les architectures 3D de circuits intégrés

The decrease of transistor’s gate length was the key driver of the development of microelectronic integrated circuits in recent decades. However, this development of microelectronic circuits has led to a greater density of interconnection lines, generating high losses, slowdowns and crosstalk on the transmitted signals, and an increase of the parasitic impedance of interconnections lines. The latter is detrimental to the power integrity of the active components in the circuit. Its increase increases the risk of developing numerical errors leading to a system’s malfunction. It is therefore necessary to reduce the impedance of the power distribution network of integrated circuits. To do this, the decoupling capacitors are used and placed hierarchically on different floors of the circuits and in their entirety (PCB, package, interposer, chip).These doctoral works are in the context of recent developments in new 3D integration solutions in microelectronics and they carry on studying new 3D capacitors, highly integrated, presenting high capacitance values (> 1 nF), and developed by using the depth of silicon interposeur level. Inspired from the Through Silicon Vias (TSV), these newly developed 3D capacitors are named Through Silicon Capacitors (TSC). They are a key element for improving the performance of the power integrated circuits because they can efficiently reduce the consumption of circuits thanks to their direct integration in silicon interposer which is used to stack chips. These 3D components allow tor reach high capacitance density up to 35 nF/mm². The issues are strategic for high speed embedded applications and more generally in an economic and societal environment aware of our energy limits. Moreover these decoupling capacitors must operate at frequencies up to 2 GHz or 4 GHz, which tend to maximize the parasitic effects which affect the energy efficiency of power distribution networks. This is made possible by optimizing their integration and by the use of copper layers with a good conductivity higher than 45 MS / m conductivity as electrodes.The technologies used to fabricate the TSC are developed by CEA-LETI and STMicroelectronics. The electrical behavior of those TSC remained hitherto little known and their performances difficult to quantify. The studies conducted in this thesis were to model these new components by taking into account the material and geometrical parameters in order to know the parasitic effects. The established electrical models have faced electrical characterizations carried out over a wide frequency range (DC to 40 GHz). This work allow to optimize the TSC architecture and their integration in a power distribution network (Power Distribution Network - NDS) prove that they are good candidate for decoupling operations.La diminution de la longueur de grille des transistors a été le moteur essentiel de l’évolution des circuits intégrés microélectroniques ces dernières décennies. Toutefois, cette évolution des circuits microélectroniques a entrainé une densification des lignes d’interconnexion, donc la génération de fortes pertes, des ralentissements et de la diaphonie sur les signaux transmis, ainsi qu’une augmentation de l’impédance parasite des interconnexions. Cette dernière est néfaste pour l’intégrité de l’alimentation des composants actifs présents dans le circuit. Son augmentation multiplie le risque d’apparition d’erreurs numériques conduisant au dysfonctionnement d’un système. Il est donc nécessaire de réduire l’impédance sur le réseau d’alimentation des circuits intégrés. Pour ce faire, les condensateurs de découplage sont utilisés et placés hiérarchiquement à différents étages des circuits et dans leur intégralité (PCB, package, interposeur, puce).Ces travaux de doctorat s’inscrivent dans le cadre des développements récents des nouvelles solutions d’intégration 3D en microélectronique et ils portent sur l’étude de nouvelles architectures de capacités 3D, très intégrées et à fortes valeurs (>1 nF), élaborées en profondeur dans l’interposeur silicium. Ces composants, inspirés des architectures de via traversant le silicium (TSV, Through Silicon Via), sont nommées Through Silicon Capacitors (TSC). Ils constituent un élément clef pour l’amélioration des performances des alimentations des circuits intégrés car elles pourront réduire efficacement la consommation des circuits grâce à cette intégration directe de composants passifs dans l’interposeur silicium qui sert d’étage d’accueil des puces. Ces composants tridimensionnels permettent en effet d’atteindre de grandes densités de capacité de 35 nF/mm². Les enjeux sont stratégiques pour des applications embarquées et à haut débit et plus généralement dans un environnement économique et sociétal conscient de nos limites énergétiques. De plus ces condensateurs de découplage doivent fonctionner à des fréquences atteignant 2 GHz, voire 4 GHz, qui tendent à maximiser les effets parasites préjudiciables aux performances énergétiques des alimentations. Ceci est rendu possible par l’optimisation de leur intégration et l’utilisation de couches de cuivre avec, une bonne conductivité supérieure à 45 MS/m, comme électrodes.Les technologies d’élaboration des condensateurs TSC ont été développées au sein du CEA-LETI et de STMicroelectronics. Leur comportement électrique restait jusqu’alors mal connu et leurs performances difficiles à quantifier. Les études menées dans cette thèse consistaient à modéliser ces nouveaux composants en prenant en compte les paramètres matériaux et géométriques afin de connaitre les effets parasites. Les modèles électriques établis ont été confrontés à des caractérisations électriques effectuées sur une large bande de fréquence (du DC à 40 GHz). Ainsi ce travail a permis d’optimiser une architecture de capacité et leur intégration dans un réseau d’alimentation d’un circuit intégré 3D a pu montrer leur efficacité pour des opérations de découplage

Characterization and modeling of new capacitors"Through Silicon Capacitors" highly integrated to reducing consumptionand to allow high frequency operating in 3D integrated circuit

La diminution de la longueur de grille des transistors a été le moteur essentiel de l’évolution des circuits intégrés microélectroniques ces dernières décennies. Toutefois, cette évolution des circuits microélectroniques a entrainé une densification des lignes d’interconnexion, donc la génération de fortes pertes, des ralentissements et de la diaphonie sur les signaux transmis, ainsi qu’une augmentation de l’impédance parasite des interconnexions. Cette dernière est néfaste pour l’intégrité de l’alimentation des composants actifs présents dans le circuit. Son augmentation multiplie le risque d’apparition d’erreurs numériques conduisant au dysfonctionnement d’un système. Il est donc nécessaire de réduire l’impédance sur le réseau d’alimentation des circuits intégrés. Pour ce faire, les condensateurs de découplage sont utilisés et placés hiérarchiquement à différents étages des circuits et dans leur intégralité (PCB, package, interposeur, puce).Ces travaux de doctorat s’inscrivent dans le cadre des développements récents des nouvelles solutions d’intégration 3D en microélectronique et ils portent sur l’étude de nouvelles architectures de capacités 3D, très intégrées et à fortes valeurs (>1 nF), élaborées en profondeur dans l’interposeur silicium. Ces composants, inspirés des architectures de via traversant le silicium (TSV, Through Silicon Via), sont nommées Through Silicon Capacitors (TSC). Ils constituent un élément clef pour l’amélioration des performances des alimentations des circuits intégrés car elles pourront réduire efficacement la consommation des circuits grâce à cette intégration directe de composants passifs dans l’interposeur silicium qui sert d’étage d’accueil des puces. Ces composants tridimensionnels permettent en effet d’atteindre de grandes densités de capacité de 35 nF/mm². Les enjeux sont stratégiques pour des applications embarquées et à haut débit et plus généralement dans un environnement économique et sociétal conscient de nos limites énergétiques. De plus ces condensateurs de découplage doivent fonctionner à des fréquences atteignant 2 GHz, voire 4 GHz, qui tendent à maximiser les effets parasites préjudiciables aux performances énergétiques des alimentations. Ceci est rendu possible par l’optimisation de leur intégration et l’utilisation de couches de cuivre avec, une bonne conductivité supérieure à 45 MS/m, comme électrodes.Les technologies d’élaboration des condensateurs TSC ont été développées au sein du CEA-LETI et de STMicroelectronics. Leur comportement électrique restait jusqu’alors mal connu et leurs performances difficiles à quantifier. Les études menées dans cette thèse consistaient à modéliser ces nouveaux composants en prenant en compte les paramètres matériaux et géométriques afin de connaitre les effets parasites. Les modèles électriques établis ont été confrontés à des caractérisations électriques effectuées sur une large bande de fréquence (du DC à 40 GHz). Ainsi ce travail a permis d’optimiser une architecture de capacité et leur intégration dans un réseau d’alimentation d’un circuit intégré 3D a pu montrer leur efficacité pour des opérations de découplage.The decrease of transistor’s gate length was the key driver of the development of microelectronic integrated circuits in recent decades. However, this development of microelectronic circuits has led to a greater density of interconnection lines, generating high losses, slowdowns and crosstalk on the transmitted signals, and an increase of the parasitic impedance of interconnections lines. The latter is detrimental to the power integrity of the active components in the circuit. Its increase increases the risk of developing numerical errors leading to a system’s malfunction. It is therefore necessary to reduce the impedance of the power distribution network of integrated circuits. To do this, the decoupling capacitors are used and placed hierarchically on different floors of the circuits and in their entirety (PCB, package, interposer, chip).These doctoral works are in the context of recent developments in new 3D integration solutions in microelectronics and they carry on studying new 3D capacitors, highly integrated, presenting high capacitance values (> 1 nF), and developed by using the depth of silicon interposeur level. Inspired from the Through Silicon Vias (TSV), these newly developed 3D capacitors are named Through Silicon Capacitors (TSC). They are a key element for improving the performance of the power integrated circuits because they can efficiently reduce the consumption of circuits thanks to their direct integration in silicon interposer which is used to stack chips. These 3D components allow tor reach high capacitance density up to 35 nF/mm². The issues are strategic for high speed embedded applications and more generally in an economic and societal environment aware of our energy limits. Moreover these decoupling capacitors must operate at frequencies up to 2 GHz or 4 GHz, which tend to maximize the parasitic effects which affect the energy efficiency of power distribution networks. This is made possible by optimizing their integration and by the use of copper layers with a good conductivity higher than 45 MS / m conductivity as electrodes.The technologies used to fabricate the TSC are developed by CEA-LETI and STMicroelectronics. The electrical behavior of those TSC remained hitherto little known and their performances difficult to quantify. The studies conducted in this thesis were to model these new components by taking into account the material and geometrical parameters in order to know the parasitic effects. The established electrical models have faced electrical characterizations carried out over a wide frequency range (DC to 40 GHz). This work allow to optimize the TSC architecture and their integration in a power distribution network (Power Distribution Network - NDS) prove that they are good candidate for decoupling operations

Méthode robuste d’extraction de paramètres de ligne de transmission en vue d’application à la caractérisation de matériaux

National audienc

Electrical Broadband Characterization Method of Dielectric Molding in 3-D IC and Results

International audienceThis paper deals with the wideband frequency molding material characterization in three dimensions stack of integrated circuits (3-D IC). This material is required as a passivation layer at the top of an element called interposer. The interposer constitutes a platform that allows to connect heterogeneous chips, for example, a radio frequency transceiver, a low-noise amplifier, and an antenna. As the molding material has been recently developed, its performance (electrical proprieties, such as permittivity and loss tangent) must be evaluated in order to predict the impact on the signals propagation. First, the process flow and fabrication steps of the 3-D stack are presented. Then, the wideband frequency characterization method based on transmission lines is described. First, this method requires highfrequency measurements using the same coplanar transmission lines with and without molding material. Second, a deembedding procedure, specifically developed for this 3-D test configuration, is performed. Next, a conformal mapping algorithm to extract the permittivity and the loss tangent of the dielectric is achieved.Finally, results are presented and discussed; for example, the molding relative permittivity is found around a value of 3.7. This value appears relatively constant up to 67 GHz. This result is promising for millimeter-wave applications, and reveals the molding as a potential good candidate for microelectronic manufacturing

Through Silicon Capacitors (TSC) for noise reduction in Power Distribution Network

International audienc