Bridging the gap between nanowires and Josephson junctions: a superconducting device based on controlled fluxon transfer across nanowires

The basis for superconducting electronics can broadly be divided between two technologies: the Josephson junction and the superconducting nanowire. While the Josephson junction (JJ) remains the dominant technology due to its high speed and low power dissipation, recently proposed nanowire devices offer improvements such as gain, high fanout, and compatibility with CMOS circuits. Despite these benefits, nanowire-based electronics have largely been limited to binary operations, with devices switching between the superconducting state and a high-impedance resistive state dominated by uncontrolled hotspot dynamics. Unlike the JJ, they cannot increment an output through successive switching, and their operation speeds are limited by their slow thermal reset times. Thus, there is a need for an intermediate device with the interfacing capabilities of a nanowire but a faster, moderated response allowing for modulation of the output. Here, we present a nanowire device based on controlled fluxon transport. We show that the device is capable of responding proportionally to the strength of its input, unlike other nanowire technologies. The device can be operated to produce a multilevel output with distinguishable states, which can be tuned by circuit parameters. Agreement between experimental results and electrothermal circuit simulations demonstrates that the device is classical and may be readily engineered for applications including use as a multilevel memory

Single-Photon Single-Flux Coupled Detectors

In this work, we present a novel device that is a combination of a superconducting nanowire single-photon detector and a superconducting multi-level memory. We show that these devices can be used to count the number of detections through single-photon to single-flux conversion. Electrical characterization of the memory properties demonstrates single-flux quantum (SFQ) separated states. Optical measurements using attenuated laser pulses with different mean photon number, pulse energies and repetition rates are shown to differentiate single-photon detection from other possible phenomena, such as multi-photon detection and thermal activation. Finally, different geometries and material stacks to improve device performance, as well as arraying methods are discussed

Multilayered Heater Nanocryotron: A Superconducting-Nanowire-Based Thermal Switch

We demonstrate a multilayer nanoscale cryogenic heater-based switch (M-hTron) that uses a normal-metal heater overlapping a thin-film superconductor separated by a thin insulating layer. The M-hTron eliminates leakage current found in three-terminal superconducting switches and applies heat locally to the superconductor, reducing the energy required to switch the device. Modeling using the energy-balance equations and the acoustic mismatch model demonstrates reasonable agreement with experiment. The M-hTron is a promising device for digital superconducting electronics that require high fan-out and offers the possibility of enhancing readout for superconducting-nanowire single-photon detectors

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below $10^{-6}$, and a 4x4 array can be fully addressed with bit select error rates of $10^{-6}$. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.Comment: 10 pages, 6 figures, submitte

Development of a scalable superconducting memory

Thesis: S.M. in Computer Science, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.Includes bibliographical references (pages 213-215).Superconducting computers promise very high computation speeds while also consuming far less power than their conventional counterparts. However, much of the progress in this field has been stymied by the lack of a scalable superconducting memory technology. In this thesis, I present the design of, and demonstrate the operation of, a superconducting nanowire-based memory cell. In contrast to existing designs, this cell operates by means of kinetic rather than geometric inductance. Thus, the cell size can be made much smaller than would otherwise be possible. With the successful operation of the single cell, paths to larger arrays are explored, and a small array demonstrated. The further development of the technology demonstrated in this work will allow for the production of large-scale superconducting processors, and the eventual development of superconducting supercomputers.by Brenden A. Butters.S.M. in Computer Scienc

Digital and Microwave Superconducting Electronics and Experimental Apparatus

The lack of a high-performance and scalable superconducting memory has been a persistent issue in the field of superconducting computing for decades. There have been many attempts at addressing this issue; however, to-date no technology has been able to completely satisfy this demand. In this work we present a novel memory design based on superconducting nanowires controlled by localized thermal effects. Initial results from this design are very promising and suggest that with some further development, our design may satisfy the need for such a superconducting memory technology. As superconducting nanowire electronics mature and become increasingly faster and more complex, the traditional reliance on off-chip microwave components has become unsustainable. In this thesis, we present the design and experimental results for a set of on-chip microwave devices, including bias tees, filters, detectors, couplers, and delay lines. In addition, by using the modeling developed for the memory, we make this set of microwave devices tunable through thermally controlling their kinetic inductance. To demonstrate the on-chip instrumentation that this library enables, a characterization of the thermal response of our tunable devices by means of an on-chip interferometer is presented. With the increasing complexity of our designs, we find ourselves in need of a new experimental apparatus to support our work. Finding no suitable solutions either commercially available or in literature, we developed a new versatile cryogenic experimental platform for nanowire electronics. The design presented here consolidates what was previously a number of discrete setups into one universal platform, while also greatly improving performance. Through the advances presented in this work, we have enabled the future realization of more complex nanowire-based superconducting electronics.Ph.D

A 2.4 GHz High Data Rate radio for pico-satellites

CubeSat is a class of popular pico-satellites that is limited in size to a standard 10x10x10cm unit. In this paper, we present a functioning High Data Rate (HDR) 2.4 GHz radio for use on a CubeSat. Current CubeSats suffer from low data rate radios and this severely limits their functionality. In this design, the operating constraints of a CubeSat have been addressed. Namely, power, wide variations in temperature, the size and weight of the components, and cost. The radio can potentially achieve bits rates in the order of 60 Mbps using 0.3W in Rx mode and 0.5W in Tx mode - with a further 2W for the power amplifier

S-band Planar Antennas for a CubeSat

This paper studies the suitability of shorted patch and CPW-feed square slot antennas for CubeSat communications. To study the effect of the CubeSat body on the antennas performance, we have simulated both antennas in the High Frequency Structure Simulator (HFSS) with and without the CubeSat body. Compared to CPWfeed square slot antenna, the shorted patch antenna achieves higher gain and wider bandwidth. We have also re-dimensioned both antennas to shift their resonant frequencies to 2.45 GHz using Quasi Newton method in HFSS. This thus enables their use in the unlicensed ISM band. The repurposed shorted patch has smaller return loss; e.g., -27.5 dB (without CubeSat), higher gain; e.g., 5.3 dBi and wider bandwidth than the repurposed CPW-feed Square slot antenna. Lastly, further enhancement in the gain of re-dimensioned CPW-feed square slot antenna shows an increase of total gain from 2 to 2.52 dB