Crypto-test-lab for security validation of ECC co-processor test infrastructure

© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksElliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.Postprint (author's final draft

Necessary and Sufficient Conditions For The Stability Of Uncertain Input-Delayed Systems

International audienceThis paper discusses stability analysis supply chain dynamics using feedback control law structure. The case study concerns the inventory control system which is considered as an input-delay system under uncertainties on customer demands with constraints related to losses of stored products. Due to the lead time of the control law and factors such as the customer demand which is supposed to be unknown, the objective is to define a control law which permits to satisfy the end-customer demand and for which the production system requirements will be completely met. The end customer demand is considered as the external perturbation. To study the stability analysis, two types of control law are proposed, both based on a feedback predictor structure. The necessary and sufficient conditions on the existence of control law are then formulated. The results demonstrate that it possible to improve the performances of the supply chain by choosing optimally the control parameters and the specifications of the production system

Impact of uncertainties of lead times and expiration dates on the stability of inventory levels in a distribution system

International audienceIn this paper, we discuss the impact of uncertainties of lead times and expiration dates on the stability of the inventory regulation problem in productions systems using feedback control law structure, in the conception phase. The inventory control system is considered as an input-delay system with uncertainties on customer demands, and positive constraints due to the specifications of the agricultural supply chain. Also, the system is characterized by the presence of delay due to the process time and the distribution time, and the perishable products are modeled by a fixed preemption rate. We have first found the necessary and sufficient conditions that prove the existence and the admissibility of the control law. Secondly, a comparative analysis of impact of production delay and expiration date uncertainties on a robust design is given. Copyright c 2019 IFA

The low area probing detector as a countermeasure against invasive attacks

© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksMicroprobing allows intercepting data from on-chip wires as well as injecting faults into data or control lines. This makes it a commonly used attack technique against security-related semiconductors, such as smart card controllers. We present the low area probing detector (LAPD) as an efficient approach to detect microprobing. It compares delay differences between symmetric lines such as bus lines to detect timing asymmetries introduced by the capacitive load of a probe. Compared with state-of-the-art microprobing countermeasures from industry, such as shields or bus encryption, the area overhead is minimal and no delays are introduced; in contrast to probing detection schemes from academia, such as the probe attempt detector, no analog circuitry is needed. We show the Monte Carlo simulation results of mismatch variations as well as process, voltage, and temperature corners on a 65-nm technology and present a simple reliability optimization. Eventually, we show that the detection of state-of-the-art commercial microprobes is possible even under extreme conditions and the margin with respect to false positives is sufficient.Peer ReviewedPostprint (author's final draft

Impact of laser attacks on the switching behavior of RRAM devices

The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, together with the rest of related works, are expected to pave the way for the development of suitable countermeasures against external attacks.Postprint (published version

RRAM Based Random Bit Generation for Hardware Security Applications

© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs still poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write operation of two parallel cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF) like primitive is implemented based on modified 1 transistor - 1 resistor (1T1R) array structure.Peer ReviewedPostprint (published version

Random masking interleaved scrambling technique as a countermeasure for DPA/DEMA attacks in cache memories

Memory remanence in SRAMs and DRAMs is usually exploited through cold-boot attacks and the targets are the main memory and the L2 cache memory. Hence, a sudden power shutdown may give an attacker the opportunity to download the contents of the memory and extract critical data. Side-channel attacks such as differential power or differential electromagnetic analysis have proven to be very effective against memory security. Furthermore, blending cold-boot attacks with DPA or DEMA can overpower even a high-level of security in cache or main memories. In this scope, data scrambling techniques have been explored and employed to improve the security, with a minor penalty in performance. Enforcing security techniques and methods in cache memories is risky because any substantial reduction in the cache memory speed might be devastating to the CPU, which is why the performance penalty must be minimal. In this paper, we introduce an improved scrambling technique which uses random masking of the scrambling vector and it is designed to protect cache memories against cold-boot and differential power or electromagnetic attacks. The technique is analyzed in terms of area, power and speed, while the level of security is evaluated through adversary models and simulated attacks

Enhanced adsorptive properties and pseudocapacitance of flexible Polyaniline-activated carbon cloth composites synthesized electrochemically in a filter-press cell

[EN] Electrochemical polymerization is known to be a suitable route to obtain conducting polymer-carbon composites uniformly covering the carbon support. In this work, we report the application of a filter-press electrochemical cell to polymerize polyaniline (PAni) on the surface of large-sized activated carbon cloth (ACC) by simple galvanostatic electropolymerization of an aniline-containing H2SO4 electrolyte. Flexible composites with different PAni loadings were synthesized by controlling the treatment time and characterized by means of Scanning Electron microscopy (SEM), X-Ray Photoelectron Spectroscopy (XPS), physical adsorption of gases, thermogravimetric analysis (TGA), cyclic voltammetry and direct current (DC) conductivity measurements. PAni grows first as a thin film mostly deposited inside ACC micro- and mesoporosity. At prolonged electropolymerization time, the amount of deposited PAni rises sharply to form a brittle and porous, thick coating of nanofibrous or nanowire-shaped structures. Composites with low-loading PAni thin films show enhanced specific capacitance, lower sheet resistance and faster adsorption kinetics of Acid Red 27. Instead, thick nanofibrous coatings have a deleterious effect, which is attributed to a dramatic decrease in the specific surface area caused by strong pore blockage and to the occurrence of contact electrical resistance. Our results demonstrate that mass-production restrictions often claimed for electropolymerization can be easily overcome.This research was funded by Spanish Ministerio de Economia y Competitividad and FEDER funds, (grants MAT2016-76595-R and RYC-2017-23618) and Generalitat Valenciana (grant PROMETEO/2018/087)Quijada, C.; Leite-Rosa, L.; Berenguer, R.; Bou-Belda, E. (2019). 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