Cubic methylammonium lead chloride perovskite as a transparent conductor in solar cell applications: An experimental and theoretical study

891-899The cubic methylammonium lead chloride (CH3NH3PbCl3) perovskite has been investigated as a transparent conductor using the experimental method and well-known density functional theory (DFT). The X-ray diffraction (XRD) of the as-prepared film confirms the good crystallinity and cubic phase of the material. The lattice constants are calculated from XRD data and compared with the lattice constants predicted employing DFT. The bandgap of the film has been studied to investigate the electronic properties and compared with the calculated bandgap of bulk CH3NH3PbCl3 using DFT. In both the cases, the bandgap has been found to be direct in nature. Also, the partial and total density of states (PDOS and TDOS) have been discussed in detail. Further, the effective mass of electrons and holes are analyzed along the high symmetry points in the brillouin zone. The UV-VIS-NIR spectrometer has been used to measure the transmittance and reflectance of CH3NH3PbCl3 film and established that films are highly transparent in visible and near IR regions. The optical properties such as dielectric functions, refractive index and absorption coefficients of bulk CH3NH3PbCl3 perovskite have been calculated in the energy range 0-5 eV. All the calculated parameters are compared with the available experimental, and the theoretical state of art results and a fair agreement has been obtained between them

Cubic methylammonium lead chloride perovskite as a transparent conductor in solar cell applications: An experimental and theoretical study

The cubic methylammonium lead chloride (CH3NH3PbCl3) perovskite has been investigated as a transparent conductor using the experimental method and well-known density functional theory (DFT). The X-ray diffraction (XRD) of the as-prepared film confirms the good crystallinity and cubic phase of the material. The lattice constants are calculated from XRD data and compared with the lattice constants predicted employing DFT. The bandgap of the film has been studied to investigate the electronic properties and compared with the calculated bandgap of bulk CH3NH3PbCl3 using DFT. In both the cases, the bandgap has been found to be direct in nature. Also, the partial and total density of states (PDOS and TDOS) have been discussed in detail. Further, the effective mass of electrons and holes are analyzed along the high symmetry points in the brillouin zone. The UV-VIS-NIR spectrometer has been used to measure the transmittance and reflectance of CH3NH3PbCl3 film and established that films are highly transparent in visible and near IR regions. The optical properties such as dielectric functions, refractive index and absorption coefficients of bulk CH3NH3PbCl3 perovskite have been calculated in the energy range 0-5 eV. All the calculated parameters are compared with the available experimental, and the theoretical state of art results and a fair agreement has been obtained between them

Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

Modeling and Simulation of a TFET-Based Label-Free Biosensor with Enhanced Sensitivity

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 1013. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications

Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

418-423The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

A surface potential-model based parameter extraction of Si–Ge-pocket n-TFET

This paper presents an algorithm based approach for TFET (Tunnel Field Effect Transistor) design. A numerous number of meta-heuristic algorithms have been used to procure the best device dimension for a Si–Ge (Silicon–Germanium) pocket n-TFET. The foremost important task is to find an alternative to hit and trails based device optimization and thereby improve the device performance by using those techniques. The algorithm based approach requires an objective function. The surface potential based models efficiently represents the device physical properties, thus surface potential based model is used as an objective function. The impact of the channel length, of the Si–Ge layer and device thickness, as well as of oxide thickness are studied by considering them as design variables. The design process involves simulating and validating the obtained dimensions in Technology Computer Aided Design (TCAD). State of art techniques are being outperformed by this algorithmic approach and out of all applied algorithms the Human Behavior Particle Swarm Optimization algorithm (HBPSO) is more accurate. An ON-current of 4.8 × 10–4 A and OFF-current of 4.8 × 10–12 A is achieved by optimizing the structure

Design and optimization of asymmetrical TFET using meta-heuristic algorithms

The complex process of semiconductor device design requires precise models and efficient optimizers. This article puts forward an Asymmetrical Hetero-Dielectric (AHD) Triple Material Gate (TMG) n-type Junctionless Tunnel Field Effect Transistor (JL-TFET). A higher gate control is achieved by using triple material in control gate and hetero-dielectric oxide, which results in high ON current and low leakage. The surface potential based model for the proposed structure is derived by analytically solving 2-D Poisson’s equation with hetero-dielectric gate oxide. This work also adopts intelligent techniques for extraction of optimal model parameters by using the derived mathematical model for the proposed JLTFET structure. The optimization technique used in this work combines the advantage of Particle Swarm Optimization (PSO) algorithm and Differential Evolution (DE) algorithm. A comparison with the conventional design process reflects that the use of optimization technique provides a novel approach to tune the process parameters. This technique outperforms the state of art design techniques and provides best accuracy along with exceptional computational efficiency. A current ratio of 1.25 × 1010 A and Point Subthreshold Swing (SS) values of 9 mV/dec and average SS of 48 mV/dec is achieved by optimizing the proposed structure

Survey on various architectures of preamplifiers for electroencephalogram (EEG) signal acquisition

Modern-day biomedical science and technology have progressed with implantable neural recording systems. There is a demand for miniaturised devices that can be emplaced into the brain for an efficient neural recording process. In contrast to the commercial gadgets, the design of implantable devices is critical, as they are placed in vital regions of the brain. The design techniques and its specifications should be properly addressed to increase the efficiency of the device. Low power is a vital parameter for the implantable devices, as it is essential that the power consumed is minimised, otherwise the battery would be rapidly drained out. The replacement of the battery comes at the cost of frequent surgery which is not a viable solution. The Electroencephalograms (EEG) are biosignals having a weak amplitude which are corrupted with electrode–skin interferences and low-frequency noise. Therefore a preamplifier stage is necessary for the analog front end of a biomedical signal acquisition system. However, the amplifier should only magnify the physiological signal with no degradation in signal‐to‐noise ratio which implies it should be capable of rejecting noise and interferences. This paper presents a comprehensive review of several low power pre‐amplifiers used in various physiological signal recording applications, along with their performance evaluation in terms of various key parameters such as gain, signal‐to-noise ratio bandwidth, common-mode rejection ratio (CMRR) and more

Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm

The main aim of the automated design methodology is to improve the design process in terms of cost, robustness and performance. Presence of noise restricts the minimum level of signal that a circuit can processed with an acceptable quality which increases the complexity of the circuit. Optimization is a time consuming and difficult tasks that involves handling wide variety of conflicting constraints or design specifications and wide range of design parameters. In this paper, Particle Swarm Optimization with an Aging Leader and challengers (ALCPSO)-based design methodology is proposed. ALCPSO is used to search the solution space for computing the constraints and design parameters with main aim of simultaneously minimizing the thermal noise and area of the circuit. In other word, the proposed design methodology incorporate noise as design specification along with other specifications which were lacking in previous automated methodology. And this methodology gives a platform to optimize both length and width of MOS transistor which will further minimize the circuit area. The computation of the ALCPSO-design methodology is performed using MATLAB and is linked to CADENCE tool with 0.18 mu m parameters technology to verify the ALCPSO-based design methodology

Effect of metal work function of asymmetric dielectric tunnel FET on its performance

In the present era, with the advancement of various non-conventional devices, hardware components dimensions are shrinking to great extent. Among those, significant part of researchers focus is drawn by Tunnel Field Effect Transistors (TFETs), because of their fundamental attribute of carriers conduction through built-in tunnelling mechanism. In this work, an asymmetric gate Tunnel Field Effect Transistor (TFET) is reported and discussed. This device structure relies on Asymmetric Dual Material Double Gate Tunnel Field Effect Transistor (ADMDG TFET) with reduced oxide thickness of 0.5 nm and optimised metal work function used at the gate terminal of the proposed TFET. For the performance analysis of such a short channel device, the relevant parameters, like threshold voltage, electric field, drain current, surface potential, Ion, Ioff and Subthreshold Swing (SS), have been considered. The proposed structure is simulated by means of the 2-D Sentaurus TCAD tool. The results report significantly low OFF-state current (Ioff), considerably improved ON-state current (Ion), and enhanced SS