Status of a DEPFET pixel system for the ILC vertex detector

We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.Comment: Invited poster at the International Symposium on the Development of Detectors for Particle, AstroParticle and Synchrotron Radiation Experiments, Stanford CA (SNIC06) 6 pages, 12 eps figure

Heavily Irradiated N-in-p Thin Planar Pixel Sensors with and without Active Edges

We present the results of the characterization of silicon pixel modules employing n-in-p planar sensors with an active thickness of 150 $\mathrm{\mu}$m, produced at MPP/HLL, and 100-200 $\mathrm{\mu}$m thin active edge sensor devices, produced at VTT in Finland. These thin sensors are designed as candidates for the ATLAS pixel detector upgrade to be operated at the HL-LHC, as they ensure radiation hardness at high fluences. They are interconnected to the ATLAS FE-I3 and FE-I4 read-out chips. Moreover, the n-in-p technology only requires a single side processing and thereby it is a cost-effective alternative to the n-in-n pixel technology presently employed in the LHC experiments. High precision beam test measurements of the hit efficiency have been performed on these devices both at the CERN SpS and at DESY, Hamburg. We studied the behavior of these sensors at different bias voltages and different beam incident angles up to the maximum one expected for the new Insertable B-Layer of ATLAS and for HL-LHC detectors. Results obtained with 150 $\mathrm{\mu}$m thin sensors, assembled with the new ATLAS FE-I4 chip and irradiated up to a fluence of 4$\times$10$^{15}\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$, show that they are excellent candidates for larger radii of the silicon pixel tracker in the upgrade of the ATLAS detector at HL-LHC. In addition, the active edge technology of the VTT devices maximizes the active area of the sensor and reduces the material budget to suit the requirements for the innermost layers. The edge pixel performance of VTT modules has been investigated at beam test experiments and the analysis after irradiation up to a fluence of 5$\times$10$^{15}\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ has been performed using radioactive sources in the laboratory.Comment: Proceedings for iWoRiD 2013 conference, submitted to JINS

Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of $10^{16}$ $\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ (1 MeV neutrons).Comment: 16 pages, 22 figure

Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at the HL-LHC

The R&D activity presented is focused on the development of new modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The performance after irradiation of n-in-p pixel sensors of different active thicknesses is studied, together with an investigation of a novel interconnection technique offered by the Fraunhofer Institute EMFT in Munich, the Solid-Liquid-InterDiffusion (SLID), which is an alternative to the standard solder bump-bonding. The pixel modules are based on thin n-in-p sensors, with an active thickness of 75 um or 150 um, produced at the MPI Semiconductor Laboratory (MPI HLL) and on 100 um thick sensors with active edges, fabricated at VTT, Finland. Hit efficiencies are derived from beam test data for thin devices irradiated up to a fluence of 4e15 neq/cm^2. For the active edge devices, the charge collection properties of the edge pixels before irradiation is discussed in detail, with respect to the inner ones, using measurements with radioactive sources. Beyond the active edge sensors, an additional ingredient needed to design four side buttable modules is the possibility of moving the wire bonding area from the chip surface facing the sensor to the backside, avoiding the implementation of the cantilever extruding beyond the sensor area. The feasibility of this process is under investigation with the FE-I3 SLID modules, where Inter Chip Vias are etched, employing an EMFT technology, with a cross section of 3 um x 10 um, at the positions of the original wire bonding pads.Comment: Proceedings for Pixel 2012 Conference, submitted to NIM A, 6 page

Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers

Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅1015\cdot 10^{15}\,neq_{\mathrm{eq}}/cm2^2

A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to $2\cdot10^{15}$\,\neqcm{} are discussed. Additionally, the etching of ICV into the front-end wafers was started. ICVs will be used to route the signals vertically through the front-end chip, to newly created pads on the backside. In the EMFT approach the chip wafer is thinned to (50--60)\,$\mu$m.Comment: Proceedings to PSD