Experimental And Theoretical Analysis Of The Electronic Behavior In Five-Coordinate Iron(iii) And Six-Coordinate Cobalt(iii) Complexes With Electroactive Phenol-Rich Ligands

Three 5 coordinate high-spin Iron(III) complexes containing pentadentate N2O5 ligands were synthesized and characterized, namely, (1) [FeIII(L1)] and (2) [FeIII(L2)]. Structural differences in ligand design,N,N,N\u27-tris(3,5-di-tert-butyl-2-hydroxybenzyl)benzene-1,2-diamine for (1) and N,N,N\u27-tris-(3,5-di-tert-butyl-2-hydroxybenzyl)-N\u27-methyl-benzene-1,2-diamine for (2), result in complexes that due to their forced geometry, asymmetry, and slightly different electronic structures are able to foster phenoxyl radicals although show a sensitive dependence to both the solvent and the electrolyte system in the cyclic voltammetry. In the presence of TBAClO4 (1) exhibits a two-electron oxidation, whereas in the presence of TBAPF6 (2), , shows three distinct phenolato/phenoxyl radical couples. Both (1) and (2) were redox-cycled 30 times without major decomposition at the surface of the electrode, indicating that the oxidized species are substitutionally inert. Three six coordinates low spin Co(III) complexes were synthesized and their electrochemical reactions were investigated in details

A Vortex Method for Bi-phasic Fluids Interacting with Rigid Bodies

We present an accurate Lagrangian method based on vortex particles, level-sets, and immersed boundary methods, for animating the interplay between two fluids and rigid solids. We show that a vortex method is a good choice for simulating bi-phase flow, such as liquid and gas, with a good level of realism. Vortex particles are localized at the interfaces between the two fluids and within the regions of high turbulence. We gain local precision and efficiency from the stable advection permitted by the vorticity formulation. Moreover, our numerical method straightforwardly solves the two-way coupling problem between the fluids and animated rigid solids. This new approach is validated through numerical comparisons with reference experiments from the computational fluid community. We also show that the visually appealing results obtained in the CG community can be reproduced with increased efficiency and an easier implementation

Conception et implémentation d'un treillis de calcul configurable à deux niveaux

Résumé De nos jours, la technologie FPGA est devenue de plus en plus puissante et complexe à un niveau que seule la technologie ASIC pouvait atteindre il y a quelques années. Les FPGA peuvent inclure plusieurs processeurs, des unités de traitement spécialisées, des réseaux sur puce pour le routage des données en interne, etc. Bien que le FPGA fonctionne à une fréquence moindre qu'un processeur à usage général, la nature parallèle de la logique matérielle permet tout de même d'opérer des algorithmes beaucoup plus rapidement. En combinant les meilleures propositions d'un système basé sur processeur ou d'un ASIC, les FPGA ont ouvert une grande flexibilité et la possibilité d'un prototypage rapide pour les ingénieurs et scientifiques de toutes les expertises. Toutefois, malgré les nombreux progrès réalisés dans la description de systèmes matériels à des niveaux d'abstraction plus élevés (des modules IP configurables, des réseaux sur puces, des processeurs configurables etc.), la réalisation d'architectures complexes est encore aujourd'hui un travail réservé aux spécialistes (typiquement des ingénieurs en conception de circuits numériques). De plus, c'est un processus relativement long (des mois, voire des années) si on considère non seulement le temps de conception de l'architecture mais encore le temps pour la vérifier et l’optimiser. De plus, les ressources disponibles augmentent à chaque nouvelle mouture, menant à des architectures de plus en plus élaborées et à une gestion de plus en plus difficile. Le FPGA proposerait alors des performances et un pouvoir de calcul inégalés, mais serait difficilement utilisable car on n'arriverait pas à extraire de façon simple et efficace toute cette puissance. Le but ultime serait d'avoir des performances du niveau matériel avec la flexibilité et la simplicité de développement du logiciel. Le projet consiste à faire la conception et l’implémentation d’une toute nouvelle architecture de type treillis permettant de traiter des algorithmes sur un grand flot de données. Les algorithmes ayant de grandes possibilités de parallélisme seraient avantagés par ce treillis. Ce treillis de calcul est configurable à deux niveaux d’abstraction. Au plus bas niveau (niveau matériel), l’architecture est constituée de divers blocs permettant de réaliser les différents chemins de données et de contrôle. Les données se propagent donc de mémoires en mémoires à travers des ALU. Ces transactions sont contrôlées par le niveau plus haut (niveau de configuration logicielle). En effet, l’utilisateur du treillis pourra venir implémenter ses algorithmes à travers de petites mémoires à instructions situées dans l’architecture. Il sera également possible de venir reconfigurer dynamiquement le comportement du treillis. On permet donc à des programmeurs logiciels d’exploiter toute la puissance d’une implémentation matérielle, sans toutefois devoir la développer en détail. Cela évite aux utilisateurs d’avoir à apprendre à exploiter les FPGA à un niveau matériel, tout en gardant confidentielle le détail interne de la dite architecture.----------Abstract Nowadays, FPGA technology has become more powerful and complex at a level that only ASIC could reach a few years ago. FPGAs can now include several processors, specialized processing units, on-chip networks for routing internal data, etc. Although the FPGA operates at a smaller frequency than a general purpose processor, the parallel nature of the hardware logic still allows algorithms to operate much faster. By combining the best parts of a system based on processor or a ASIC, FPGAs have allowed a great deal of flexibility and the possibility of rapid prototyping for engineers and scientists of all expertise. However, despite the many advances in hardware systems described at higher levels of abstraction, the implementation of complex architecture is still a job for specialists (electronic engineers designing digital circuits). Moreover, it is a relatively long process (months or years) if we consider not only the time to design the architecture but also the time to verify and optimize it. In addition, available resources are increasing in each new FPGA version, leading architectures to become more elaborate and management more difficult. The FPGA proposes very high performance and unrivaled computing power, but may become obsolete because it is difficult to extract in a simple and effective way all that power. The ultimate goal would be to have hardware performance with software development simplicity and flexibility. The project involves the design and implementation of a new architecture (mesh type) for processing algorithms on a large data stream. Algorithms with great potential for parallelism would benefit from this lattice. The mesh is configurable at two levels of abstraction. At the lowest level (hardware level), the architecture consists of various blocks supporting the different data paths and control structures. The data thus propagate from memories to memories through ALUs. These transactions are controlled by a higher representation (software level). In fact, the user can implement algorithms on the lattice through small memories placed within the architecture. With the proposed structure, it is also possible to dynamically reconfigure the behavior of the lattice. It thus allows software programmers to harness the power of a hardware implementation, without further notice. This prevents users from having to learn how to use the FPGA while allowing to keep confidential the architecture itself. This work is part of an industrial partnership with a company financing the project with a MITACS internship. The company manufactures and markets frame grabbers operating at high frequencies and offering high resolutions. These cards are already using FPGAs with an important part of these circuits being unused logic. Customers are asking to use this logic to perform preprocessing algorithms. However, most of them would be unable to use it effectively and without harming the rest of the logic required for proper operation of the board. In addition, the partner does not want to disclose the source code of the architecture implemented in the FPGA. The relevance of the proposed project is therefore justified by the fact that it would be possible to deliver boards with the architecture (in addition to the logic already used). The customer would only specify his high-level applications

Evaluation and effects of temperature in optoelectronic waveguide devices

Condensé français comportement thermique de dispositifs opto-électroniques à guides d'ondes -- Optoelectronic components in optical fiber communications -- Liquid-crystal temperature measurements -- Instantaneous blow-up experiments -- Absorption measurements -- Thermal modelling -- Correlation of electro-optic data and overstress tests

Réseau social de soutien par les pairs et adaptation scolaire et psychosociale des jeunes : examen des liens bidirectionnels en contexte de transition primaire-secondaire

Cette étude vise à déterminer la présence et la direction des liens (possiblement bidirectionnels) entre le réseau social de soutien par les pairs (étendue, qualité, stabilité) et l'adaptation scolaire et psychosociale des élèves durant la transition primaire-secondaire. 393 élèves de sixième année du primaire constituent l'échantillon de base de cette étude. Les données ont été recueillies à quatre reprises sur une période de 2 ans et demie. Les résultats montrent, d'une part, que la qualité du réseau social prédit les symptômes dépressifs et les difficultés de comportement extériorisées dans le temps et d'autre part, que les résultats scolaires et les difficultés de comportement extériorisés prédisent la stabilité du réseau social de soutien dans le temps

Multiple-scales analysis of photonic crystal waveguides

The multiple-scales method is used to derive a scalar differential equation that describes the envelopes of photonic crystal waveguide modes. For a photonic crystal heterostructure waveguide and an air core photonic crystal waveguide, the mode frequencies calculated from the envelope approximation and full numerical simulations agree to 9% in the worst case when compared to the frequency difference of the band edges. The single-mode and cutoff width conditions for a photonic crystal waveguide are predicted and verified

Microbial narrow-escape is facilitated by wall interactions

Cells have evolved efficient strategies to probe their surroundings and navigate through complex environments. From metastatic spread in the body to swimming cells in porous materials, escape through narrow constrictions - a key component of any structured environment connecting isolated microdomains - is one ubiquitous and crucial aspect of cell exploration. Here, using the model microalgae Chlamydomonas reinhardtii, we combine experiments and simulations to achieve a tractable realization of the classical Brownian narrow-escape problem in the context of active confined matter. Our results differ from those expected for Brownian particles or leaking chaotic billiards and demonstrate that cell-wall interactions substantially modify escape rates and, under generic conditions, expedite spread dynamics.</p

Multiple-scales analysis of photonic crystal waveguides

The multiple-scales method is used to derive a scalar differential equation that describes the envelopes of photonic crystal waveguide modes. For a photonic crystal heterostructure waveguide and an air core photonic crystal waveguide, the mode frequencies calculated from the envelope approximation and full numerical simulations agree to 9% in the worst case when compared to the frequency difference of the band edges. The single-mode and cutoff width conditions for a photonic crystal waveguide are predicted and verified

Tunneling Activities Detection Using Machine Learning Techniques, Journal of Telecommunications and Information Technology, 2011, nr 1

Tunnel establishment, like HTTPS tunnel or related ones, between a computer protected by a security gateway and a remote server located outside the protected network is the most effective way to bypass the network security policy. Indeed, a permitted protocol can be used to embed a forbidden one until the remote server. Therefore, if the resulting information flow is ciphered, security standard tools such as application level gateways (ALG), firewalls, intrusion detection system (IDS), do not detect this violation. In this paper, we describe a statistical analysis of ciphered flows that allows detection of the carried inner protocol. Regarding the deployed security policy, this technology could be added in security tools to detect forbidden protocols usages. In the defence domain, this technology could help preventing information leaks through side channels. At the end of this article, we present a tunnel detection tool architecture and the results obtained with our approach on a public database containing real data flows