Fractionary Charged Particles Confronting Lepton Flavor Violation and the Muon's Anomalous Magnetic Moment

In light of the result published by the Fermilab Muon $(g-2)$ experiment, we investigate a simple model that includes particles of fractional electric charges: a colour-singlet fermion and a scalar with charges $2/3e$ and $1/3e$, respectively. The impact of these particles on the muon anomalous magnetic moment are examined, particularly the restrictions on their Yukawa couplings with the light leptons. Given that lepton flavor violation processes impose stringent constraints on certain scenarios beyond the Standard Model, we asses the one-loop contribution of the new particles to $(g-2)$ in order to identify regions in the parameter space consistent with the Fermilab results and compatible with the current and projected limits on the branching ratio $Br(\mu \rightarrow e \gamma)$. Taking into account the current lower bound for the masses of fractionary charged particles, which is around 634 GeV, we show that the mass of the scalar particle with fractional charge must exceed 1 TeV and may be discovered in future collider experiments. Finally, we also study the validity of our model in light of the QCD lattice results on the muon $(g-2)$.Comment: 14 pages, 5 figure

Adaptive runtime-assisted block prefetching on chip-multiprocessors

Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.Peer ReviewedPostprint (author's final draft

Transforming “The National Autonomous University of Mexico (UNAM)” Into a Lighthouse-Project of Sustainability

AbstractUNAM is the oldest and one of the most prestigious universities in the Americas. The main campus of the university is home of about 300 000 students and covers an area of about 4 square-kilometres in the south of Mexico City. UNAM is also one of the biggest electricity consumers in Mexico-City. More than 70 Million kWh electricity are consumed yearly, producing about 49 000 tons of CO2 emission. Within the paper we will show that this could be changed with a high financial and educational profit.As UNAM has no heating and only a few cooling systems, lighting is by far the biggest use of electricity. The existing lighting system is extremely inefficient while providing unsatisfactory illumination in some places. The UNEP Centre on Sustainable Production and Consumption (CSCP) together with Büro Ö-quadrat devised a project which demonstrates how UNAM can benefit from an upgrade to a highly efficient lighting system. What makes the project unique is that the results are not based on theoretical calculations but were corroborated by implementation results of a highly efficient lighting system in four different areas (a foyer, classrooms, a library and a workshop) and the measurement of the electricity savings. Within these four areas the average electricity saving was 84% and the combined pay-back time was 2.7 years. Based on the empirical results and an analysis of 10 UNAM-buildings a master plan was developed for the entire university campus. Here the objective was to establish the broad strategic principles for a successful lighting system upgrade, as well as the necessary budget and savings that could be achieved. The results demonstrate that an initial investment of US$14 million would result in electricity costs savings of US$ 68 million over the 20 year lifetime of the upgraded lighting system. About thirty per cent of the electricity consumed in UNAM today could be saved with a high profit on investment.In a second step we show that most of the remaining electricity consumption could be produced by solar energy. The Feed-in Tariff system in Germany has led to a high capacity of PV-production and lowered the cost for PV-systems: In May 2013 a 40kW PV system, including all parts for the mounting, can be bought in Europe for a price of about 800 Euro/kW. Assuming that on 2% of the UNAM-area PV-systems would be installed, these systems could produce about 23 GWh with lower costs compared to the electricity price UNAM has to pay.Combining the investment for efficient lighting and PV-systems, about 60% (or about 29 000 tons) of the CO2-emissions of UNAM could be saved with a high rate of return.Best of all: What would be a more convincing way to educate 60 000 students every year about sustainability than a practical example of highly efficient lighting system and powered by solar energy? UNAM could be a light house for many other universities and schools

Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications

High performance computing (HPC) applications have parallel code sections that must scale to large numbers of cores, which makes them sensitive to serial regions. Current supercomputing systems with heterogeneous or asymmetric CMPs (ACMP) combine few high-performance big cores for serial regions, together with many low-power lean cores for throughput computing. The low requirements of HPC applications in the core front-end lead some designs, such as SMT and GPU cores, to share front-end structures including the instruction cache (I-cache). However, little work exists to analyze the benefit of sharing the I-cache among full cores, which seems compelling as a solution to reduce silicon area and power. This paper analyzes the performance, power and area impact of such a design on an ACMP with one high-performance core and multiple low-power cores. Having identified that multiple cores run the same code during parallel regions, the lean cores share the I-cache with the intent of benefiting from mutual prefetching, without increasing the average access latency. Our exploration of the multiple parameters finds the sweet spot on a wide interconnect to access the shared I-cache and the inclusion of a few line buffers to provide the required bandwidth and latency to sustain performance. The projections with McPAT and a rich set of HPC benchmarks show 11% area savings with a 5% energy reduction at no performance cost.The research was supported by European Unions 7th Framework Programme [FP7/2007-2013] under project Mont-Blanc (288777), the Ministry of Economy and Competitiveness of Spain (TIN2012-34557, TIN2015-65316-P, and BES-2013-063925), Generalitat de Catalunya (2014-SGR-1051 and 2014-SGR-1272), HiPEAC-3 Network of Excellence (ICT-287759), and finally the Severo Ochoa Program (SEV-2011-00067) of the Spanish Government.Peer ReviewedPostprint (author's final draft

Rebalancing the core front-end through HPC code analysis

There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional desktop and server workloads, different from parallel applications commonly run in HPC. In this work, we focus on the HPC code characteristics and processor front-end which factors around 30% of core power and area on the emerging lean-core type of processors used in HPC. Separating serial from parallel code sections inside applications, we characterize three HPC benchmark suites and compare them to a traditional set of desktop integer workloads. HPC applications have biased and mostly backward taken branches, small dynamic instruction footprints, and long basic blocks. Our findings suggest smaller branch predictors (BP) with the additional loop BP, smaller branch target buffers (BTB), and smaller L1 instruction caches (I-cache) with wider lines. Still, the aforementioned downsizing applies only to the cores meant to run parallel code. The difference between serial and parallel code sections in HPC applications points to an asymmetric CMP design, with one baseline core for sequential and many HPCtailored cores designed for parallel code. Predictions using Sniper simulator and McPAT show that an HPC-tailored lean core saves 16% of the core area and 7% of power compared to a baseline core, without performance loss. Using the area savings to add an extra core, an asymmetric CMP with one baseline and eight tailored cores has the same area budget as a symmetric CMP composed out of eight baseline cores demanding 4% more power and providing 12% shorter execution time on average.Postprint (author's final draft

Análisis multivariante del rendimiento académico de ingeniería en estadística informática

El presente trabajo esta orientado a encontrar los factores cuantitativos y cualitativos que determinan y explican el Rendimiento Académico del estudiante así como el análisis de dichos factores y la explicación de los mismos y también se intentará medirlo a través de un Indice Relativo y de Eficiencia. En el primer capítulo se hará una explicación sobre lo que se entiende por Rendimiento Académico, algunos conceptos del mismo y técnicas para medirlo. En el cuerpo del trabajo se incluirá las técnicas, entre ellas el análisis univariado y multivariado y el Índice Relativo y de Eficiencia, procedimientos y resultados con los que se realizó el estudio y con los que se sustenta la conclusione

Resistencia a flexión de un concreto sustituyendo el agregado grueso con 3% y 5% de plástico PET

El presente trabajo de investigación como propósito fundamental fue determinado la resistencia a la flexión de una viga de concreto f´c=210 kg/cm2, al sustituir en un 3% y 5% de Plástico PET fragmentado para incrementar la resistencia a la flexión. La metodología de la presente investigación es del tipo correlacional, experimental puro; correlacional porque experimenta el comportamiento del concreto cuando se le sustituye el Plástico PET fragmentado y es del tipo experimental porque estudia el comportamiento de la resistencia a la flexión del concreto f´c=210 kg/cm2, cuando se le sustituye el Plástico PET fragmentado. Se realizaron 27 ensayos de rotura de la resistencia a la flexión de las vigas a los 7, 14 y 28 días de curado del concreto, sustituyendo el Plástico PET fragmentado en 3% y 5% del volumen del concreto realizando las comparaciones con una viga patrón con 3 ensayos por cada uno. Los resultados favorables fueron a los 28 días de curado del concreto donde la resistencia a la flexión de la muestra patrón llegó a los 35.63 kg/cm2, la sustitución del 3% fue de 34.63 kg/cm2 y del 5% a 36.25 kg/cm2, donde se incrementó la resistencia a la flexión en un 1.68%.Tesi