Characterizing the Enterprise of Military Systems Acquisition

Student research poste

Eits: Combinatorics, Potential and Genre

Eits is a work of fiction, a non-traditional novel whose structure is largely determined by an Oulipian-style constraint. The constraint in Eits is culled from the album names and song titles of the band Explosions in the Sky. Each album corresponds to a chapter in the novel, and the language of each album title must be used in some way as an introduction to each chapter. Within each chapter (album), song titles correspond to numbered sections where each title must appear as is in the first sentence of that section. This not only dictates, to some degree, the direction of the text that will follow, but, looking ahead, the title of the next section will dictate where this section must arrive. From this, a narrative naturally takes shape. Albums/chapters appear chronologically, according to each album\u27s release date, and within each album/chapter, songs/sections appear in the order they do on the album. This is, perhaps, the most straightforward way of ordering the received language of the constraint, the possibilities beyond this exponential. Eits is a novel that shifts in form, providing a texture to the space and reading experience of the novel, all in hopes of creating a space in which content and form inform and push each other to new limits. Eits is never satisfied to settle on one form for too long, and it is in the movement between forms that the narrative develops in interesting ways. Eits demonstrates the combinatoric possibilities inherent in language, and this exploration of potential highlights the reciprocal relationship between writing and reading. As Eits builds upon a limited language set, it explores and exploits the combinatory possibilities that language allows for both writer and reader. It demonstrates that all combinatoric potentialities, visible or not, always co-exist in the same time and space, and in this infinite space, individuals are invited to be writers and readers in simultaneity

The Prudential Spirit of Community Youth Survey: A Survey of High School Students on Community Involvement

Most of today\u27s high-school teens (62%) feel their communities are good or very good places to live. But more say that conditions in their communities are getting worse (30%) than getting better (25%). Crime and violence are the most pressing problems facing communities today, according to 36% of students. Other areas of concern are drug and alcohol abuse (cited by 18%), education (7%), economic problems (7%) and lack of youth programs (6%). More than six teens in ten (62%) say the solutions to such problems lie in individual action rather than government programs. Only one in three (33%) favor government programs

Enterprise Risk and Product Development Portfolios

Student research poste

Identifying Leverage Points in Defense System Acquisition

LAI Webinar Knowledge Exchange Even

A Partial TMR Technique for Improving Reliability at a Low Hardware Cost in FPGAs

The flexibility combined with the computational capabilities of FPGAs make them a very attractive solution for space-based computing platforms. However, SRAM-based FPGAs are susceptible to radiation effects, including Single Event Upsets. In order to increase the fault tolerance of FPGA designs, fault mitigation techniques, such as Triple Module Redundancy, can be applied. Such techniques, however, can be excessive in terms of hardware costs. This work investigates the tradeoffs between fault mitigation techniques for FPGA designs and the corresponding costs of such mitigation. A particular focus is placed upon identifying design components that serve to benefit most from the application of fault tolerance techniques, and investigating the tradeoffs associated with applying mitigation to these most sensitive design sections

Voter Insertion Techniques for Fault Tolerant FPGA Design

Triple Modular Redundancy (TMR) is a common reliability technique for FPGA designs used in radiation environments. TMR consists of triplicating a design and inserting voters to mask errors using redundancy. This paper will investigate the automatic placement of voters in TMR designs. In particular, it will introduce three algorithms for determining where to insert synchronization voters and compare the area and timing impact of these algorithms on FPGA designs. It will be shown that the placement of synchronization voters in a triplicated design can have an important impact on the area and timing characteristics of the resulting design. The algorithms presented in this paper give results that increase the critical path length of a design when adding TMR voters by as little as 3% to as much as 50%

Reducing Rad-Hard Memories for FPGA Configuration Storage on Space-bound Payloads

FPGA use in space-based applications is becoming more common. Radiation-hardened (rad-hard) memories are typically used to store configuration data for programming the FPGA and performing bitstream scrubbing to remove errors in the system that occur from single event upsets (SEUs). Since device densities for the latest FPGAs are growing at a faster rate than rad-hard memories, it is becoming more difficult to reliably store the FPGA configuration data without using a large number of memories. We present a method for cutting the use of rad-hard memories necessary to support the use of the latest FPGA technologies in space-based applications. This paper describes a solution to this memory problem which utilizes FPGA partial reconfiguration, with device self-scrubbing, and bitstream compression to create a minimally sized bootstrap design that has a memory footprint that is a fraction of the size of the original design. This bootstrap design is stored locally, and the remaining design elements can be reconfigured as necessary from a remote location. The resulting prototype design yields a compressed bitstream that at less than 2% the size of the bitstream for largest FPGA currently on the market

Meta-Data and Interface Synthesis Techniques for Improving Design Productivity in Reconfigurable Computing

This paper demonstrates improvements in design productivity for reconfigurable computing which are accomplished through a novel IP reuse strategy. It presents a set of extensions to the IP-XACT XML specification that define the temporal behavior of cores and describes how these extensions are used in the Ogre synthesis system to simplify design complexity and thereby reduce design time. Design productivity improvement is demonstrated by reducing design time for software radio designs from days to hours

IP Delivery for FPGAs Using Applets and JHDL

This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of applicationspecific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor