A class-based clustering static compaction technique for combinational circuits

Static compaction based on test vector merging is a very simple and efficient technique. However, for a highly incompatible test set, merging achieves little reduction. In this paper, we propose a new static compaction technique in which a test vector is decomposed into its atomic components before it is processed. In this way, a test vector that is originally incompatible with all other test vectors in a given test set can be eliminated if its components can be merged with other test vectors

A class-based clustering static compaction technique for combinational circuits

Static compaction based on test vector merging is a very simple and efficient technique. However, for a highly incompatible test set, merging achieves little reduction. In this paper, we propose a new static compaction technique in which a test vector is decomposed into its atomic components before it is processed. In this way, a test vector that is originally incompatible with all other test vectors in a given test set can be eliminated if its components can be merged with other test vectors

A static test compaction technique for combinational circuits based on independent fault clustering

Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm

On test vector reordering for combinational circuits

The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such a way that it reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique

A Class-based Clustering Static Compaction Technique for Combinational Circuits

Static compaction based on test vector merging is a very simple and efficient technique. However, for a highly incompatible test set, merging achieves little reduction. In this paper, we propose a new static compaction technique in which a test vector is decomposed into its atomic components before it is processed. In this way, a test vector that is originally incompatible with all other test vectors in a given test set can be eliminated if its components can be merged with other test vectors

Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this paper, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms

On Test Vector Reordering for Combinational Circuits

The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique

A Class-based Clustering Static Compaction Technique for Combinational Circuits

Static compaction based on test vector merging is a very simple and efficient technique. However, for a highly incompatible test set, merging achieves little reduction. In this paper, we propose a new static compaction technique in which a test vector is decomposed into its atomic components before it is processed. In this way, a test vector that is originally incompatible with all other test vectors in a given test set can be eliminated if its components can be merged with other test vectors