Separating Control and Data Flow: Methodology and Automotive System Case Study

In this document we propose to study the control/data flow separation design methodology, using Scade and Mode-Automata, and its application in the design of an automotive system. This methodology allows to facilitate the specification of different kinds of systems and to have a better readability. It also separates the study of the different parts by using the most appropriate existing tools for each of them. To do that, we study a cruise control system with GPS which makes possible the control of a car speed depending on its position given by a GPS. This system combines both control and data processing and can be specified using our methodology. The goal of this work consists in presenting the application of our methodology on a real system and studing its advantages notably for formal verification

Introducing Control in the Gaspard2 Data-Parallel Metamodel: Synchronous Approach

In this document, we study the introduction of control in the Gaspard2 application UML metamodel by using the synchronous reactive system principles. This allows to take the change of running mode into account in the case of data parallel applications, and to study more general ways of mixing control and data parallel processing. Our study is applied to a particular context using two different models, exclusively dedicated to the process of computation or control. The computation part represents the Gaspard2 application metamodels based on the Array-OL language. This Language is often used to specify the data dependencies and the potential parallelism in intensive signal processing applications manipulating multidimensional data. The control part is represented by an automaton structure based on the Mode-Automata concept which makes it possible to clearly identify the different modes of a task and the switching conditions between modes. For this kind of applications, mixing control and data parallel processing, we propose an UML metamodel allowing to better visualize and control the construction of the system by clarifying, at a height abstraction level, the various relations and the possible interactions of this system. The proposed UML metamodel makes it possible to describe and to model the control automata, the different running modes and the link between control and computation parts. It also allows to clearly separate control and data parts by respecting the concurrency, the parallelism, the determinism and the compositionality of the Gaspard2 models

FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar

The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are to be evaluated in practical domains such as the automotive sector for reactive cruise control and anti-collision radar. We choose to define specific IPs using FPGA techniques to cover this application domain. This paper presents the implementation of such a complex and safety application on a single FPGA. The target system is composed of a reactive cruise control, a detection radar and the associated treatments

New Biosensor Design Based on Photonic Crystal Core-shell Rods Defects for Detecting Glucose Concentration

In this paper, an ultra compact photonic crystal (PhC) biosensor for detecting glucose concentration using resonant microcavity (RMC), sandwiched by two inline quasi-waveguides is investigated. The RMC is used as sensing region. It consisted of 7x7 core/shell (C/S) rod defects and 14 functionalized holes. The basic structure is formed by air holes arranged in hexagonal lattice in silicon (Si) background. The sensing mechanism of our biosensor is to detect the resonant wavelength shift, which is caused by the change of the refractive index (RI) of the shell layer and active holes filled with the analyte sample of glucose solution. The plane wave expansion (PWE) and finite difference time domain (FDTD) methods are chosen to analyze and simulate the performance of the suggested structure. The FDTD results reveal high sensitivity of 624.7904 nm/RIU with high linearity and quality factor. The presented sensor has a simple design and is easy to manufacture. In addition, the total size of the presented device is 92.65 µm2 which is very small for nanotechnology based sensing

A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

Invariants intégraux pour l'indexation d'images omnidirectionnelles

Dans cette étude, nous nous intéressons à la localisation d'un robot mobile par indexation d'images omnidirectionnelles. La localisation est qualitative et le robot doit déterminer la pièce dans laquelle il se trouve. L'indexation est réalisée à partir d'invariants intégraux calculés sur les images omnidirectionnelles. Notre méthode utilise l'intégrale de Haar dans laquelle nous intégrons un modèle du capteur omnidirectionnel. L'approche intégrale nous permet de prendre en compte simplement la géométrie du capteur ainsi que les déplacements du robot pour le calcul des invariants. La robustesse de cette nouvelle méthode à des déplacements dans une pièce est supérieure à une méthode basée sur l'histogramme

Non-conventional yeasts as sources of ene-reductases for the bioreduction of chalcones

Thirteen Non-Conventional Yeasts (NCYs) have been investigated for their ability to reduce activated C=C bonds of chalcones to obtain the corresponding dihydrochalcones. A possible correlation between bioreducing capacity of the NCYs and the substrate structure was estimated. Generally, whole-cells of the NCYs were able to hydrogenate the C=C double bond occurring in (E)-1,3-diphenylprop-2-en-1-one, while worthy bioconversion yields were obtained when the substrate exhibited the presence of a deactivating electron-withdrawing Cl substituent on the B-ring. On the contrary, no conversion was generally found, with a few exceptions, in the presence of an activating electron-donating substituent OH. The bioreduction aptitude of the NCYs was apparently correlated to the logP value: Compounds characterized by a higher logP exhibited a superior aptitude to be reduced by the NCYs than compounds with a lower logP value

MEMORY REQUIREMENTS FOR HARDWARE IMPLEMENTATION OF THE H.264 ENCODER MODULES

For a hardware implementation of any image processing algorithm, it is necessary to study the input/output of each processing module  even  before  studying  the  internal  architecture  of  these modules. And  that  to  prepare  a  simulation  platform, with internal and external memory, necessary  to  load and  to prepare  the  input  for  the modules. These memories are also used as intermediate  component  between  the  different modules  to  provide  the  possibility  of  parallelism.  In  this work we  give  the architecture  of  internal  and  external  memory  used  by  the  H.264  encoder  in  order  to  develop  a  simulation  platform  for processing modules. This platform can be realized in FPGA platform chosen according to the memory requirements