MODELING OF GROWTH RATES OF SELECTIVE EPITAXIAL GROWTH (SEG) AND EPITAXIAL LATERAL OVERGROWTH (ELO) OF SILICON IN THE SIH2CL2-HCL-H2 SYSTEM

A semi-empirical model for the growth rate of selective epitaxial silicon(SEG) in the Dichlorosilane-HC1-Hz system that represents the experimenltal data has been presented. All epitaxy runs were done using a Gemini-I LPCVD pancake reactor. Dichlorosilane was used as the source gas and hydrogen as the carrier gas. Hydrogen Cllloride(HC1) was used to ensure that no nucleation took place on the oxide. The growth rate expression was considered to be the sum of a growth term dependent on the partial pressures of Dichlorosilane and hydrogen, and an etch berm that varies as the partial pressure of HC1. The growth and etch terms were found to have an Arrhenius relation with temperature, with activation energies of 52kcal/mol and 36kcal/mol respectively. Good agreement was obtained with experimental data. The variation of the selectivity threshold was correctly predicted, which had been a problem with earlier models for SEG growth rates. SEG/ELO Silicon was grown from 920-970°C at 40 and 150 torr pressures for a variety of HCI concentrations. In addition previous data collected by our research group at 820-1020°C and 40-150torr were used in the model

C-AMTE: A location mechanism for flexible cache management in chip multiprocessors

This paper describes Constrained Associative-Mapping-of-Tracking-Entries (C-AMTE), a scalable mechanism to facilitate flexible and efficient distributed cache management in large-scale chip multiprocessors (CMPs). C-AMTE enables fast locating of cache blocks in CMP cache schemes that employ one-to-one or one-to-many associative mappings. C-AMTE stores in per-core data structures tracking entries to avoid on-chip interconnect traffic outburst or long distance directory lookups. Simulation results using a full system simulator demonstrate that C-AMTE achieves improvement in cache access latency by up to 34.4%, close to that of a perfect location strategy. © 2010 Elsevier Inc. All rights reserved

Silicon etch rate enhancement by traces of metal

We report the effect of nickel and tungsten contamination on the etch behavior of silicon. This is studied in a molecular beam setup, where silicon is etched by XeF2 and Ar+ ions. The etch process is directly monitored by the SiF4 reaction products which leave the surface. The effect of contamination appears very pronounced after the ion beam is switched off: it leads to a temporary enhancement of the spontaneous etch rate on a time scale of 500 s. With traces of contamination on the order of 0.01 ML, the etch rate may be enhanced by a factor of 2 for W and somewhat less for Ni. It is concluded that the contamination moves into the silicon by diffusion to vacancies created by the Ar+ ions. For 1 keV Ar+ ions the contamination moves to a depth of 25 Å, comparable to the penetration depth of the ions. After etching a 170 Å thick layer, the catalytic effect of contamination is reduced to less than 5%. A simple model, which describes the measured effect of contamination very well, indicates that only 3% of the contamination is removed when a monolayer of silicon is etched away. Besides this catalytic effect there are indications that contamination can also lower the etch rate under certain conditions, because of the formation of silicides. From the measurements no conclusions could be drawn about the underlying mechanism of etch rate enhancement. © 1999 American Vacuum Society