Calculation of Cu/Ta interface electron transmission and effect on conductivity in nanoscale interconnect technology

Resistivity augmentation in nanoscale metal interconnects is a performance limiting factor in integrated circuits. Here we present calculations of electron scattering and transmission at the interface between Cu interconnects and their barrier layers, in this case Ta. We also present a semiclassical model to predict the technological impact of this scattering and find that a barrier layer can significantly decrease conductivity, consistent with previously published measurements.Comment: To appear in Appl. Phys. Lett., Nov. 2009. Replaced with version accepted for publication, clarifies discussion of semiclassical model. Conclusions unchange

An evolutionary psychology model of ego, risk, and cognitive dissonance

I propose a novel model of the human ego (which I define as the tendency to measure one’s value based on extrinsic success rather than intrinsic aptitude or ability). I further propose the conjecture that ego so defined both is a non-adaptive by-product of evolutionary pressures, and has some evolutionary value as an adaptation (protecting self-interest). I explore ramifications of this model, including how it mediates individuals’ reactions to perceived and actual limits of their power, their ability to cope with risk and uncertainty, and how this model may interpolate between rational choice models and cognitive psychology. I develop numerous examples and applications, including poverty traps, to demonstrate the model’s predictive power to elucidate a broad range of social phenomena. [December 2018: Updated version to submit for publication. Expanded Sections 4 and 5.1, revised Section 5.7

Transport properties and electrical device characteristics with the TiMeS computational platform: application in silicon nanowires

Nanoelectronics requires the development of a priori technology evaluation for materials and device design that takes into account quantum physical effects and the explicit chemical nature at the atomic scale. Here, we present a cross-platform quantum transport computation tool. Using first-principles electronic structure, it allows for flexible and efficient calculations of materials transport properties and realistic device simulations to extract current-voltage and transfer characteristics. We apply this computational method to the calculation of the mean free path in silicon nanowires with dopant and surface oxygen impurities. The dependence of transport on basis set is established, with the optimized double zeta polarized basis giving a reasonable compromise between converged results and efficiency. The current-voltage characteristics of ultrascaled (3 nm length) nanowire-based transistors with p-i-p and p-n-p doping profiles are also investigated. It is found that charge self-consistency affects the device characteristics more significantly than the choice of the basis set. These devices yield source-drain tunneling currents in the range of 0.5 nA (p-n-p junction) to 2 nA (p-i-p junction), implying that junctioned transistor designs at these length scales would likely fail to keep carriers out of the channel in the off-state

Highly parallelizable electronic transport calculations in periodic Rhodium and Copper nanostructures

We extend the highly-parallelizable open-source electronic transport code TRANSEC to perform real-space atomic-scale electronic transport calculations with periodic boundary conditions in the lateral dimensions. We demonstrate the use of TRANSEC in periodic Cu and Rh bulk structures and in large periodic Rh point contacts, in preparation to perform calculations of reflection probability across Rh grain boundaries

Simulation of junctionless Si nanowire transistors with 3 nm gate length

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of similar to 1 nm wire diameter and similar to 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration. (C) 2010 American Institute of Physics. (doi:10.1063/1.3478012