Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip

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An Emulation Platform for Evaluating the Reliability of Deep Neural Networks

In recent years, Deep Neural Networks have been increasingly adopted by a wide range of applications characterized by high-reliability requirements, such as aerospace and automotive. In this paper, we propose an FPGA-based platform for emulating faults in the architecture of DNNs. The approach exploits the reconfigurability of FPGAs to mimic faults affecting the hardware implementing DNNs. The platform allows the emulation of various kinds of fault models enabling the possibility to adapt to different types, devices, and architectures. In this work, a fault injection campaign has been performed on a convolutional layer of AlexNet, demonstrating the feasibility of the platform. Furthermore, the errors induced in the layer are analyzed with respect to the impact on the whole network inference classification

A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiationsensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell

Evaluating Reliability against SEE of Embedded Systems: A Comparison of RTOS and Bare-metal Approaches

Embedded processors are widely used in critical applications such as space missions, where reliability is mandatory for the success of missions. Due to the increasing application complexity, the number of systems using Real-Time Operating Systems (RTOSs) is quickly growing to manage the execution of multiple applications and meet timing constraints. However, whether operating systems or bare-metal applications provide higher reliability is still being determined. We present a comprehensive reliability analysis of software applications running on a device with bare-metal and FreeRTOS against the same faults based on fault models derived from a proton test. Additionally, the FreeRTOS system has been evaluated with a set of software applications dedicated to evaluating specific RTOS functions, providing an additional evaluation for operations crucial for a real-time operating system

In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops

Nowadays, radiation-induced Single Event Transients are a leading cause of critical errors in CMOS nanometric integrated circuits. In this work, we propose a workflow for analyzing and mitigating nanometric CMOS integrated circuits to radiation-induced transient errors. The analysis phase starts with the developed Rad-Ray tool for mimicking the passage of the radiation particles through the silicon matter of the cells to identify the features of the generated transient pulses. The tool is integrated with an electrical simulator to evaluate the dynamic behavior of the transient pulses inserted and propagated in the circuit. A tunable mitigation solution is proposed by inserting the filtering block before the storage element, tuned based on the duration and amplitude of the expected transient pulse, identified in the analysis phase. Experimental results are achieved by applying the proposed approach on the 45 nm Flip-Flop component available in the FreePDK design kit, comparing the Dynamic Error Rate for the original Flip-Flop and the mitigated one which shows a reduction of sensitivity up to 56% with respect of the original version, with negligible degradation of performances

A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor

Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead

On the Evaluation of the PIPB Effect within SRAM-based FPGAs

SRAM-based FPGAs are widely used in mission critical applications. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, Single Event Transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose an approach for evaluating the Propagation-induced Pulse Broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. The proposed methodology is applicable to any recent technology to provide SET analysis, necessary for an efficient mitigation technology. Experimental results achieved from a set of benchmarks are compared with fault injection experiments executed on a 28 nm SRAM-based FPGA to demonstrate the effectiveness of our technique

On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing

We propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to 45-nm 3D LUT and the results show a 37% reduction in failure rate

SEU Evaluation of Hardened-by-Replication Software in RISC-V Soft Processor

The interest of the space industry around soft processors is increasing. However, the advantages in terms of costs and customizability provided by soft processors are countered by the reliability issues deriving by Single Event Effects, especially Single Event Upsets. Several techniques have been proposed to tackle these issues, both at the hardware- and software levels. Software approaches rely on replicating data and computations to cope with SEUs affecting the memory where the binary code is stored. Thanks to open licenses, RISCV solutions are steadily growing in popularity among the set of available soft processors. In this works, we present a reliability evaluation of four different benchmarks running on the RI5CY soft processor implemented on SRAM-based FPGAs. The reliability of the baseline and hardened-by-replication versions of the software benchmarks are evaluated against SEUs induced faults both at the software and hardware architecture levels through fault injection campaigns in the microprocessor memory and configuration memory, respectively. Results assess how the adoption of the hardening-by-replication technique at the software level slightly improves reliability against software related faults but degrades reliability against architectural faults, making it an inefficient solution when it is not combined with hardware robustness

A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit

Radiation-induced soft errors have become a significant reliability challenge in modern CMOS logic. The main concern for safety-critical applications such aerospace is due to Single Event Transient (SET) effects. SETs are exacerbated by the technology scaling of modern technologies especially when they are adopted in harsh environments. This paper evaluates the SET sensitivity of state-of-the-art floating gate configurable logic circuit and proposes a novel methodology for filtering a SET pulse generated inside the logic cells by increasing the charge sharing effect on the sensitive node of a cell due to remapping of its configurable switches. Experimental results, performed with radiation particle simulation on several benchmark circuits implemented in a 130nm floating-gate device demonstrate an improvement in filtering SET effects of more than 24% on the average with negligible delay degradation