'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling
of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits
must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology.
The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiationsensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell