535 research outputs found

    Efficiency and risk in sustaining Chinaā€™s food production and security: Evidence from micro-level panel data analysis of Japonica rice production

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    Sustainable food production and food security are always challenging issues in China. This paper constructs a multi-element two-level constant-elasticity-of-substitution (CES) model to assess technological progress in, and its contribution to, japonica rice production in China. The results show that the speed of technological progress in the production of japonica rice on average was 0.44% per annum in 1985ā€“2013, and technological progress has contributed significantly to the growth of japonica rice production in China. Robustness checks show that the results appear to be sensitive to which sub-sample is used. Labour and some other inputs are found to be significant but negative, especially during the middle sampling period of 1994ā€“2006 and in eastern and western regions. This has important policy implications on the impact of rural-to-urban migration and farmersā€™ human development. View Full-Tex

    A note on (Ī±,Ī²)-derivations

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    AbstractWe show that every multiplicative (Ī±,Ī²)-derivation of a ring R is additive if there exists an idempotent eā€² (eā€²ā‰ 0,1) in R satisfying the conditions (C1)ā€“(C3): (C1) Ī²(eā€²)Rx=0 implies x=0; (C2) Ī²(eā€²)xĪ±(eā€²)R(1-Ī±(eā€²))=0 implies Ī²(eā€²)xĪ±(eā€²)=0; (C3) xR=0 implies x=0. In particular, every multiplicative (Ī±,Ī²)-derivation of a prime ring with a nontrivial idempotent is additive. As applications, we could decompose a multiplicative (Ī±,Ī²)-derivation of the algebra Mn(C) of all the nƗn complex matrices into a sum of an (Ī±,Ī²)-inner derivation and an (Ī±,Ī²)-derivation on Mn(C) given by an additive derivation f on C

    The worldā€™s earliest Aral-Sea type disaster: the decline of the Loulan Kingdom in the Tarim Basin

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    The presented data are accessible in the PANGAEA database, https://doi.pangaea.de/10.1594/PANGAEA.871173.Remnants of cities and farmlands in Chinaā€™s hyperarid Tarim Basin indicate that environmental conditions were significantly wetter two millennia ago in a region which is barren desert today. Historical documents and age data of organic remains show that the Loulan Kingdom flourished during the Han Dynasty (206 BCEā€“220 CE) but was abandoned between its end and 645 CE. Previous archaeological, geomorphological and geological studies suggest that deteriorating climate conditions led to the abandonment of the ancient desert cities. Based on analyses of lake sediments from Lop Nur in the eastern Tarim Basin and a review of published records, we show that the Loulan Kingdom decline resulted from a man-made environmental disaster comparable to the recent Aral Sea crisis rather than from changing climate. Lop Nur and other lakes within the Han Dynasty realm experienced rapidly declining water levels or even desiccation whilst lakes in adjacent regions recorded rising levels and relatively wet conditions during the time of the Loulan Kingdom decline. Water withdrawal for irrigation farming in the middle reaches of rivers likely caused water shortage downstream and eventually the widespread deterioration of desert oases a long time before man initiated the Aral Sea disaster in the 1960s.Funding was provided by Chinaā€™s NSF projects (40830420, 41471003), the State key project (2003BA612A-06ā€“15) of the Ministry of Science and Technology of China and the German Research Foundation (DFG grant Mi 730/16-1). We thank two anonymous reviewers who provided very constructive comments on an earlier version of this paper.Peer Reviewe

    CHARACTERIZATION OF A MICROPUMP ACTUATED BY TERNARY TiNiCu SHAPE MEMORY THIN FILMS

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    ABSTRACT Thin film SMAs have the potential to became a primary actuating mechanism for micropumps. In this study, a micropump driven by TiNiCu shape memory thin film is designed and fabricated. The micropump is composed of a TiNiCu/Si bimorph driving membrane, a pump chamber and two inlet and outlet check valves. The thickness, surface morphology and phase transformation property of TiNiCu film have been characterized by scanning electron microscope (SEM), atomic force microscopy (AFM), differential scanning calorimeters (DSC). Driving capacity of TiNiCu/Si biomorphic driving membrane has been investigated. The film surface shows a smooth and featureless morphology without any cracks, and the hysteresis width āˆ†T of TiNiCu film is about 10 ĀŗC. By using the recoverable force of TiNiCu thin film, the actuation diaphragm realizes reciprocating motion effectively. Experimental results show that the micropump driving by TiNiCu film has good performance, such as high working frequency, stable driving capacity, and long fatigue life time

    A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform

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    In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) is proposed. The main focus of the scheme is on reducing the number and period of clock cycles for the DWT computation with little or no overhead on the hardware resources by maximizing the inter- and intrastage parallelisms of the pipeline. The interstage parallelism is enhanced by optimally mapping the computational load associated with the various DWT decomposition levels to the stages of the pipeline and by synchronizing their operations. The intrastage parallelism is enhanced by decomposing the filtering operation equally into two subtasks that can be performed independently in parallel and by optimally organizing the bitwise operations for performing each subtask so that the delay of the critical data path from a partial-product bit to a bit of the output sample for the filtering operation is minimized. It is shown that an architecture designed based on the proposed scheme requires a smaller number of clock cycles compared to that of the architectures employing comparable hardware resources. In fact, the requirement on the hardware resources of the architecture designed by using the proposed scheme also gets improved due to a smaller number of registers that need to be employed. Based on the proposed scheme, a specific example of designing an architecture for the DWT computation is considered. In order to assess the feasibility and the efficiency of the proposed scheme, the architecture thus designed is simulated and implemented on a field-programmable gate-array board. It is seen that the simulation and implementation results conform to the stated goals of the proposed scheme, thus making the scheme a viable approach for designing a practical and realizable architecture for real-time DWT computation

    A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

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    In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is enhanced by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and synchronizing their operations. The intra-stage parallelism is enhanced by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel and minimizing the delay of the critical path of bit-wise adder networks for performing the filtering operation. To validate the proposed scheme, a circuit is designed, simulated, and implemented in FPGA for the 2-D DWT computation. The results of the implementation show that the circuit is capable of operating with a maximum clock frequency of 134 MHz and processing 1022 frames of size 512 Ɨ 512 per second with this operating frequency. It is shown that the performance in terms of the processing speed of the architecture designed based on the proposed scheme is superior to those of the architectures designed using other existing schemes, and it has similar or lower hardware consumption
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