Dynamic formation of spherical voids crossing linear defects

A predictive model for the evolution of porous Ge layer upon thermal treatment is reported. We represent an idealized etched dislocation core as an axially symmetric elongated hole and computed its dynamics during annealing. Numerical simulations of the shape change of a completely spherical void via surface diffusion have been performed. Simulations and experiments show individual large spherical voids, aligned along the dislocation core. The creation of voids could facilitate interactions between dislocations, enabling the dislocation network to change its connectivity in a way that facilitates the subsequent annihilation of dislocation segments. This confirms that thermally activated processes such as state diffusion of porous materials provide mechanisms whereby the defects are removed or arranged in configurations of lower energy. This model is intended to be indicative, and more detailed experimental characterization of process parameters such as annealing temperature and time, and could estimate the annealing time for given temperatures, or vice versa, with the right parameters.Comment: 7 pages, 3 figure

Chemical composition of nanoporous layer formed by electrochemical etching of p-type GaAs

Abstract : We have performed a detailed characterization study of electrochemically etched p-type GaAs in a hydrofluoric acid-based electrolyte. The samples were investigated and characterized through cathodoluminescence (CL), X-ray diffraction (XRD), energy-dispersive X-ray spectroscopy (EDX), and X-ray photoelectron spectroscopy (XPS). It was found that after electrochemical etching, the porous layer showed a major decrease in the CL intensity and a change in chemical composition and in the crystalline phase. Contrary to previous reports on p-GaAs porosification, which stated that the formed layer is composed of porous GaAs, we report evidence that the porous layer is in fact mainly constituted of porous As2O3. Finally, a qualitative model is proposed to explain the porous As2O3 layer formation on p-GaAs substrate

Ingénierie de défauts liés à l’hétéroépitaxie de Ge sur Si: Substrats virtuels à base de germanium poreux pour le photovoltaïque

Today’s photovoltaics market is dominated by silicon-based technology, as it is inexpensive and mature. Solar cells (SCs) based on III-V compound semiconductors have attained the highest reported efficiency of any photovoltaic devices to date. However, the high cost for producing these cells is limiting their use to concentrated photovoltaic (CPV) space applications. The market demand will be higher if the cost of III-V solar cells was reduced and adapted for low-concentration applications. The major contribution in the cost for III-V SCs scaled up to high volume manufacturing is associated with the cost of the substrate. This could substantially be reduced, if a Ge/Si substrate were used, especially that Ge offers advantages in strength and cost over GaAs substrates while providing a similar lattice constant. However, the integration of these lattice-mismatched materials (Ge/Si) remains difficult and presents physical and technological challenges. Threading dislocations introduced inside the germanium layers have a detrimental effect on device performances. In this research, we seek to accommodate the effects of the lattice mismatch by introducing a voided germanium interface layer (porous Ge layer) on the silicon substrate to intercept dislocations and prevent them from reaching the active layers of the device. The nanovoids are formed by a scalable process, through dislocation-selective electrochemical deep etching and thermal annealing, which leads to the formation of a continuous Ge layer, in which, a large portion of the original threading dislocations are pinned and annihilated close to a free surface. The fabrication process of these virtual substrates meets the industrial criteria: Monocrystalline on the surface, defect-fee, epi-ready and obtained at the wafer scale by a low cost process. The averaged threading dislocation density is reduced by over three orders of magnitude, from ~107 cm−2 to ~104 cm−2 for 1.5 µm thick Ge layers, which is considered very low for such a thin epitaxial layer. Our technique may be applied to realize virtual substrates for multi-junctions solar cells on a Si support. As a result, significant cost savings become possible if the bulk Ge substrates can be replaced with our virtual analogs consisting of micron-thick Ge buffers grown on Si wafers.L'électricité d'origine photovoltaïque constituera une composante majeure des apports énergétiques domestiques dans les prochaines décennies. Aujourd'hui et malgré des rendements records, le coût des cellules solaires à base de matériau III-V sur germanium (Ge) est toujours trop dispendieux pour démocratiser cette technologie au niveau grand public. Le prix du substrat de Ge s’élève à plus de 50 % du prix de la cellule au complet alors que moins de 1% du substrat de Ge constitue la zone active du composant où le courant est généré. Une alternative serait donc d’intégrer une couche épitaxiale de Ge sur un support mécanique ou un substrat semi-conducteur à faible coût comme le silicium. Cependant, l’épitaxie de Ge sur substrat de Si présente des barrières physiques et technologiques. Le fort désaccord en paramètre de maille (4,2%) engendre des dislocations et contribuent majoritairement à dégrader le rendement des cellules. Dans le cadre de cette thèse, nous avons développé de nouvelles architectures de substrat virtuels de germanium-sur-silicium à base de porosification électrochimique. Les dislocations sont éliminées de la couche épitaxiale par un procédé de nano structuration thermo-électrochimique, permettant de créer une barrière de nano-cavités qui piège les dislocations. Le procédé de fabrication de ces substrats virtuels répond aux critères industriels : Monocristallins en surface, exempts de défauts, epi-ready et réalisés sur des substrats de grande taille par un procédé faible coût. La densité de dislocations moyenne est réduite de plus de trois ordres de grandeur, de ~ 107 cm-2 à ~ 104 cm-2 pour des couches de Ge de 1,5 μm d'épaisseur, ce qui est considéré comme très faible pour une couche épitaxiale aussi mince.L'utilisation de ces procédés simples, par anodisation électrochimique et recuit thermique adéquat, s’est révélée très efficace et innovante permettant de réduire significativement le coût des cellules photovoltaïques à base de matériau III-V sur substrat silicium, ainsi que leurs intégrations probables dans le marché grand public

Low cost Ge/Si virtual substrate engineering for III-V multi-junction solar cell

International audienc

Low cost Ge/Si virtual substrate through dislocation trapping by nanovoids

International audienceA low-cost method to reduce the threading disloca-tions density (TDD) in relaxed germanium (Ge) epilayers grown on silicon (Si) substrates is presented. Ge/Si sub-strate was treated with post epitaxial process to create a region with a high density of nanovoids in Ge layer which act as a barrier for threading dislocations propagation

Ge/Si Virtual Substrate for III-V multi-junction solar cells

International audienc

Dynamic formation of spherical voids crossing linear defects

7 pages, 3 figuresInternational audienceA predictive model for the evolution of porous Ge layer upon thermal treatment is reported. We represent an idealized etched dislocation core as an axially symmetric elongated hole and computed its dynamics during annealing. Numerical simulations of the shape change of a completely spherical void via surface diffusion have been performed. Simulations and experiments show individual large spherical voids, aligned along the dislocation core. The creation of voids could facilitate interactions between dislocations, enabling the dislocation network to change its connectivity in a way that facilitates the subsequent annihilation of dislocation segments. This confirms that thermally activated processes such as state diffusion of porous materials provide mechanisms whereby the defects are removed or arranged in configurations of lower energy. This model is intended to be indicative, and more detailed experimental characterization of process parameters such as annealing temperature and time, and could estimate the annealing time for given temperatures, or vice versa, with the right parameters

Suspended NbN superconducting resonator for reducing intrinsic losses

International audienceSuperconducting coplanar waveguide (CPW) microwave resonators are crucial elements in Photon detectors, Quantum-limited parametric amplifiers, Narrow-band filters, Read-out, interconnect in quantum processors and Hybrid devices, connecting solid-state spins with superconducting circuits [1-3]. In the quantum regime, the dominant loss mechanism for high-Q superconducting resonators can be attributed to parasitic two-level systems (TLSs) in the dielectrics. Interface TLSs are common by products of the fabrication process, often introduced by impurities associated with Si surfaces [3]. To reduce intrinsic losses, we employ isotropic deep reactive-ion etching (DRIE) of Si substrate to create suspended NbN superconducting resonators (SSR).In this study, thin films of niobium (Nb) and niobium nitride (NbN) are deposited on Si substrate by a DC magnetron sputtering system. The influence of the N2/Ar gas ratio, the deposition current, the substrate bias potential on the superconducting critical temperature of the films are investigated. Plasma etching of Nb and NbN in a SF6 and Cl2-BCl3 gas plasma is studied using an inductively coupled plasma (icp) reactor. Parametric studies on the effects of total gas flow rate and chamber pressure on the edge angles and etch rates are reported. Finally, the suspended NbN superconducting resonator is fabricated and will be tested. This could be applied to the fabrication of superconducting qubits in integrated circuits, offering a path towards longer qubit coherence times.Reference:[1] Landig et al. Coherent spin–photon coupling using a resonant exchange qubit. Nature 560, 179–184 (2018)[2] Tosi et al. Silicon quantum processor with robust long-distance qubit couplings. Nat Commun 8, 450 (2017)[3] Bruno et al. Reducing intrinsic loss in superconducting resonators by surface treatment and deep etching of silicon substrates, Appl. Phys. Lett. 106, 182601 (2015)[4] Kennedy et al. Tunable Nb Superconducting Resonator Based on a Constriction Nano-SQUID Fabricated with a Ne Focused Ion Beam, Phys. Rev. Applied 11, 014006 (2019)

High-quality Ge/Si virtual substrates fabricated by a low cost and scalable process

International audienceIn this presentation, we propose a new defect engineering strategy in highly mismatched hetero-epitaxy to simultaneously achieve low dislocation density and epi-ready Ge/Si virtual substrate using a highly scalable process. By self-assembling nanovoids around the Ge/Si interface from both sides through dislocation-selective electrochemical deep etching and thermal annealing, a continuous Ge layer is obtained, in which, a large portion of the original threading dislocations are pinned and annihilated close to a free surface, giving a new configuration so-called “Nanovoids-based Ge/Si Virtual Substrate (NVS)”