Editorial: clock/frequency generation circuits and systems

1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2Department of Electronics, University of Pavia, 27100 Pavia, Italy 3Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5Electrical Engineering Department, University of California, Los Angeles, CA 90095, US

Clock/Frequency Generation Circuits and Systems

1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2Department of Electronics, University of Pavia, 27100 Pavia, Italy 3Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5Electrical Engineering Department, University of California, Los Angeles, CA 90095, US

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively