PENGARUH PELATIHAN, PENGEMBANGAN SUMBER DAYA INSANI DAN KOMPENSASI SYARIAH TERHADAP KINERJA KARYAWAN PADA BANK SUMSEL BABEL SYARIAH KC PALEMBANG

Dalam penelitian ini bertujuan untuk menguji pengaruh pelatihan, pengembangan sumber daya insani dan kompensasi syariah terhadap kinerja karyawan pada Bank Sumsel Babel Syariah KC Palembang. Lokasi Penelitian ini fokus pada Bank Sumsel Babel Syariah KC Palembang, yang merupakan bank berbasis syariah yang memberikan bentuk pelatihan, pengembangan sumber daya insani serta pemberian kompensasi untuk melaksanakan berbagai kegiatan yang berhubungan dengan pencapaian perusahaan. Jenis penelitian adalah penelitian kuantitatif, dengan data yang diperoleh melalui penyebaran kuisioner kepada karyawan Bank Sumsel Babel Syariah KC Palembang. Jumlah sampel sebanyak 32 sampel yang dipilih berdasarkan metode purposive sampling dari 57 karyawan Bank Sumsel Babel Syariah KC Palembang. Adapun Teknik analisis data yang digunakan adalah uji validitas, uji reliabilitas, uji asumsi klasik, regresi linier berganda dan uji hipotesis serta pengolahan data menggunakan SPSS (Statistical Package for the Social Sciences). Penelitian ini menemukan bahwa pelatihan berpengaruh terhadap kinerja karyawan di Bank Sumsel Babel Syariah KC Palembang, berpengaruh sebesar 0.804 atau 80.40% dan signifikan dengan angka signifikansi 0.028 < α = 0.05. pengembangan sumber daya insani berpengaruh terhadap kinerja karyawan di Bank Sumsel Babel Syariah KC Palembang, berpengaruh sebesar 0.698 atau 69.80% dan signifikan dengan angka signifikan 0.041 < α = 0.05. kompensasi syariah berpengaruh terhadap kinerja karyawan di Bank Sumsel Babel Syariah KC Palembang, berpengaruh sebesar 0.260 atau 26% dan signifikan dengan angka signifikansi 0.010 < α = 0.05

WAKEUP-SET SCHEDULING FOR LARGE INSTRUCTION WINDOW PROCESSORS BY

Out-of-order processor performance is limited by instruction scheduler size. Current “issue buffer ” based instruction scheduler implementations do not scale with the size of the instruction window. We propose distributing the functions of instruction wakeup and selection-issue across separate structures specialized for each task and conclude that (1) limiting the “bandwidth of wakeup ” to the width of the pipeline does not significantly impact performance, (2) the number of instructions awaiting wakeup by a particular physical tag does not significantly increase with the scheduler size, and (3) the number of instructions which are ready for issue is considerably smaller than the size of the scheduler itself. Thus we propose the wakeup-set scheduler. Instructions with unsatisfied dependencies are placed in a bankable, limited sized wakeup-sets array where they await the production of their operands. A separate ready-instruction queue holds the instructions which are ready to issue for execution. As register values are produced, they index their wakeup-sets to discover waiting instructions. When an instruction’s dependencies are satisfied, it moves from its wakeup-set to the ready-instruction queue from where it may be issued for execution. We present a

Exploiting Postdominance for Speculative Parallelization

Task-selection policies are critical to the performance of any architecture that uses speculation to extract paral-lel tasks from a sequential thread. This paper demonstrates that the immediate postdominators of conditional branches provide a larger set of parallel tasks than existing task-selection heuristics, which are limited to programming lan-guage constructs (such as loops or procedure calls). Our evaluation shows that postdominance-based task selection achieves, on average, more than double the speedup of the best individual heuristic, and 33 % more speedup than the best combination of heuristics. The specific contributions of this paper include, first, a description of task selection based on immediate post-dominance for a system that speculatively creates tasks. Second, our experimental evaluation demonstrates that ex-isting task-selection heuristics based on loops, procedure calls, and if-else statements are all subsumed by compiler-generated immediate postdominators. Finally, by demon-strating that dynamic reconvergence prediction closely ap-proximates immediate postdominator analysis, we show that the notion of immediate postdominators may also be useful in constructing dynamic task selection mechanisms.

P Perilaku Politik Masyarakat Desa Tempang Tiga Kecamatan Langowan Utara Kabupaten Minahasa Pada Pemilihan Umum Tahun 2024: Perilaku politik masyarakat desa tempang

Derajat partisipasi masyarakat di Indonesia salah satunya dapat dilihat dari perilaku politik pemilih dalam menentukan pilihannya pada saat pemilihan umum. Artikel ini mengkaji tentang perilaku politik masyarakat pada pemilihan umum tahun 2024. Dengan menggunakan pendekatan, kajian ini akan medeskripsikan perilaku politik pemilih masyarakat yang ada di Desa Tempang Tiga Kecamatan Langowan Utara Kabupaten Minahasa. Kajian dilakukan dengan menggunakan pendekatan yang dikemukakan oleh Dennis Kavanagh, tentang analisis perilaku politik pemilih yaitu melalui pendekatan sosiologis, pendekatan psikologis, dan pendekatan rasional. Temuan penelitian menggambarkan perilaku pemilih yang ada di Desa Tempang Tiga Kecamatan Langowan Utara Kabupaten Minahasa dari pendekatan sosiologis masih di pengaruhi oleh faktor etnisitas. Sedangkan pendekatan psikologis menggambarkan masyarakat dalam berpartisipasi juga dipengaruhi oleh factor-faktor seperti identifikasi partai, orientasi kandidat, dan orientasi isu/tema kampanye. Sementara dari pendekatan rasional, tergambar perilaku pemilih ada juga yang didasarkan dari pertimbangan untung dan rugi. Temuan penelitian menggambarkan juga bahwa sebagian besar perilaku politik pemilih Desa Tempang Tiga Kecamatan Langowan Utara Kabupaten Minahasa dominan di pengaruhi oleh ketokohan dari kandidat

Synchronizing store sets (SSS): Balancing the benefits and risks of inter-thread load speculation

Speculative parallelization (SP) enables a processor to extract multiple threads from a single sequential thread and execute them in parallel. For speculative parallelization to achieve high performance on integer programs, loads must speculate on the data dependences among threads. Techniques for speculating on inter-thread data dependences have a first-order impact on the performance, power, and complexity of SP architectures. Synchronizing predicted inter-thread dependences enables aggressive load speculation while minimizing the risk of misspeculation. In this paper, we present store set synchronization, a complexityeffective technique for speculating on inter-thread data dependences. The store set synchronizer (SSS) predicts store-load dependences using store sets and enforces those predicted dependences using recently proposed techniques for dynamic register synchronization. The key insight behind store set synchronization is that predicted dependences carried through store sets can be treated exactly like the dependences carried through architectural registers. By balancing the benefits and risks of load speculation, the SSS increases performance, conserves power, and reduces complexity. On integer benchmarks the SSS increases performance by as much as 56 % and by 20 % on average. The SSS also reduces the average rate of dependence violations by 80%, which conserves power and dramatically decreases the number of threads squashed due to dependence violations. Furthermore, the low rate of dependence violations mitigates the need for costly disambiguation hardware such as per-thread load queues. We show that replacing the associative load queues with filtered load re-execution in an SSS-equipped system decreases performance by just 3%.

Confidence based out-of-order renaming for speculatively multithreaded processors

Speculatively multithreaded processors find parallelism by speculatively fetching and renaming dynamic flows of instructions from (perhaps) widely seperated parts of the program flow graph. These processors must handle inter-thread register dependences. The approach followed in this paper is to dynamically identify the consumers of interflow register mappings that will be (but have not yet been) produced in a logically earlier thread and then to dynamically awaken those consumers as soon as the mapping they are waiting for is produced. The main contribution of this paper is the design and evaluation of the inter-thread register renaming and synchronization mechanisms for a speculatively multithreaded processor that does not need compiler support. Our scheme is realizable, aggressive, and flexible and achieves speedups within about 10 % of those achievable by an oracle. We find that inter-thread synchronization mechanisms can and must use path confidence information so that the producers of register mappings can awaken consumer instructions at just the right time, neither so early that the producer is on a misspredicted branch path, nor so late as to add latency to the critical path. We also demonstrate that a relatively straight-forward predictor can find the set of consumer instructions that must wait without being overly conservative.