Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction

This paper presents the design of a compact pro-tocol for fixed-latency, high-speed, reliable, serial transmissionbetween simple field-programmable gate arrays (FPGA) devices.Implementation of the project aims to delineate word boundaries,provide randomness to the electromagnetic interference (EMI)generated by the electrical transitions, allow for clock recov-ery and maintain direct current (DC) balance. An orthogonalconcatenated coding scheme is used for correcting transmissionerrors using modified Bose–Chaudhuri–Hocquenghem (BCH)code capable of correcting all single bit errors and most ofthe double-adjacent errors. As a result all burst errors of alength up to 31 bits, and some of the longer group errors,are corrected within 256 bits long packet. The efficiency of theproposed solution equals 46.48%, as 119 out of 256 bits arefully available to the user. The design has been implementedand tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kitwith a data rate of 28.2 Gbps. Sample latency analysis has alsobeen performed so that user could easily carry out calculationsfor different transmission speed. The main advancement of thework is the use of modified BCH(15, 11) code that leads to higherror correction capabilities for burst errors and user friendlypacket length

SMX and front-end board tester for CBM readout chain

The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, front-end board (FEB), or a full detector module. The software written in Python may easily be integrated with higher-level testing software

Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems

FPGA-based data acquisition and processing systems play an important role in modern high-speed, multichannel measurement systems, especially in High-Energy and Plasma Physics. Such FPGA-based systems require an extended control and diagnostics part corresponding to the complexity of the controlled system. Managing the complex structure of registers while keeping the tight coupling between hardware and software is a tedious and potentially error-prone process. Various existing solutions aimed at helping that task do not perfectly match all specific requirements of that application area. The paper presents a new solution based on the XML system description, facilitating the automated generation of the control system’s HDL code and software components and enabling easy integration with the control software. The emphasis is put on reusability, ease of maintenance in the case of system modification, easy detection of mistakes, and the possibility of use in modern FPGAs. The presented system has been successfully used in data acquisition and preprocessing projects in high-energy physics experiments. It enables easy creation and modification of the control system definition and convenient access to the control and diagnostic blocks. The presented system is an open-source solution and may be adopted by the user for particular needs

High-Performance Lightweight HLS Generator Module of Normally Distributed Random Numbers in FPGAs

This paper focuses on the problem of high-performance streaming random number generation in the range of uniform and normal distributions in FPGAs. Our work is focused on lightweight implementation, suitable for a wide range of FPGAs. First, we review the existing types of random generation modules. Next, in this paper we present the construction of the designed generator. We divide it into two sections: Stream Uniform Numbers Generator Implementation and Cumulative Distribution-Based Stream Gaussian Generator. Each design step was verified in the scope of the quality of the output data, especially regarding the produced distributions. The results obtained are compared with existing solutions. We mainly consider resource utilization and throughput. We also add our quality factor, which is an effective utilization of FPGAs. Despite quality results, our modules were implemented using a high-level synthesis language (C/C++), contrary to typical hardware description level (HDL) approaches. It provides the opportunity to implement the proposed algorithms on CPUs. It was tested with positive results, thus highlighting the versatility of the solution that is unavailable in terms of HDL implementations. Our designed generators were confirmed to stand out for their satisfactory performance while occupying low logical resources