9 research outputs found

    Linearity of Bulk-Controlled Inverter Ring VCO in Weak and Strong Inversion

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    Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology

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    Broadband powerline communication systems using Orthogonal Frequency Division Multiplexing (OFDM) can utilize existing power lines to transmit data packets alongside power distribution. Recent standards focus towards high speed multi-media in-house streaming. With improvements towards robustness and throughput new standards increase the speed and reliability of in-house powerline systems. A very different approach is the use of powerline communication systems in a deep drilling environment where temperatures of more than 150°C and pressure levels up to 30 000 psi are present. Typical applications in this environment usually do not require more than several kbit/ys per node and are more reliant on a stable and continuous connection. Here, a powerline communication system can reduce the amount of wiring needed and increase communication robustness significantly. This work provides a harsh environment suitable, reliable and standard compliant communication ASIC that is manufactured in XFAB 180 nm Silicon-On-Insulator (SOI) technology allowing operating temperatures of up to 175°C. The die size is 5.25 mm x 5.25 mm and contains a complete Homeplug 1.0 communication stack with an environment for boot, interfacing and debugging. The data rate is as high as 6.1 Mbit/s using the fastest transmission mode and reaches the theoretical maximum of 0.55 Mbit/s in the robust OFDM (ROBO) mode which is of particular interest for harsh environment applications. To the best of the authors knowledge, this is the first OFDM-based powerline communication ASIC which is particularly designed for harsh environment.© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works

    Floating-Gate UVMOS inverter

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    This paper describes a novel technique for implementing low-voltage/low-power digital circuits. The threshold and supply voltage can be set to desired values while exposing the chip to UV-light. UV-light activated conductances between the power supply-rails and the floating gates are used to program the desired threshold shift. The FGUVMOS inverter is described and measurements are shown

    Ultra Low-Voltage Digital Floating-Gate UVMOS (FGUVMOS) Circuits

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    This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits. The threshold and supply voltage can be set to desired values while exposing the chip to UV-light. UV-light activated conductances between the power supply-rails and the floating gates are used to program the desired threshold shift. The FGUVMOS inverter is described and measurements are shown

    Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

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    In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2 x improvement in read noise margin while it improves write margin by 3 x for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations. (C) 2013 Elsevier Ltd. All rights reserved
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