Optimal Deteriorating Inventory Models for Varies Supply Life Cycles

Agriculture items, such as fruits and vegetables, have different supply and demand characteristics during a harvest period. Fruits supply in the first and end of harvest time are not reliable so sometimes supply are not available when needed. Fruits demand is different during harvest season. In the first harvest season, demand depends on price and at the end of harvest time, the demand depends on presentation of the items. In this study, inventory deteriorating items models for the first and the end of the harvest season are developed. Since closed-form solutions cannot be derived from the models, a Genetic Algorithm and a heuristic method are used to solve the problems. A numerical example and sensitivity analysis are conducted to illustrate the model and get insights. The sensitivity analysis shows that the supplier will increase his price when supply is not reliable at the early harvest period. The results show that the unreliable supply is susceptible to the total cost at the end of the harvest period

Key Users and Box Office Analysis in an Interest Based Virtual Community

In recent years, with the growth of the Internet technology, the users of virtual community not only play the role of the information receiver but also a very important one to provide information. However, there is large amount of information aggregated daily and therefore information overloading has become a very serious problem. Under this situation, how to find information efficiently is also a very important issue. In this paper, we believe users in a virtual community may affect each other, especially those with high influence who have been called as Key Users. Therefore, we observe the biggest virtual community of movies on the Internet which is named IMDb (The Internet Movie Database). An architecture also has been proposed that combines Social Networks Analysis and the features of IMDb to discover those users who have high influence in the virtual community. We collected 17 months (January 2010 to May 2011) from IMDb including 17 366 users and 243 074 reviews. By applying the method we proposed, there are about 22 key users and 111 reviews were discovered. We also use the box office of the movies to justify our results

Low temperature lithographically patterned metal oxide transistors for large area electronics

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 167-184).Optically transparent, wide bandgap metal oxide semiconductors are a promising candidate for large-area electronics technologies that require lightweight, temperature-sensitive flexible substrates. Because these thin films retain relatively high carrier mobilities even in an amorphous state, metal oxide-based field effect transistors (FETs) can be processed at near-room temperatures. Compared to amorphous silicon FETs, which are the dominant technology used in display backplanes, metal oxide FETs have been demonstrated with higher charge carrier mobilities, higher current densities, and faster response performance. In this thesis we present a low-temperature ('1000C), scalable, fully lithographic process for top-gate, bottom-contact amorphous zinc indium oxide FETs using parylene, a room-temperature-deposited CVD polymer, as gate dielectric. Electrical characteristics were compared for FETs of varying device dimensions (W, L) using a standard set of extracted device parameters. We show in both simulation and experiment that the FET threshold voltage can be modified by varying the channel thickness alone, without requiring the additional complexity of multiple channel materials or different dopings. The baseline lithographic process was further developed to enable the integration of FETs of different channel thicknesses, and hence threshold voltages, on a single substrate. The availability of FETs with different threshold voltages allows the implementation of enhancement-depletion (E/D) logic circuits that have faster speeds and smaller device areas than single-VT topologies. Using the two-VT lithographic process, we fabricated integrated E/D inverters that operate at VDD as low as 3V with gains > 20 and symmetric noise margins ~1.2V. Furthermore, we demonstrated integrated 11-stage and 21-stage E/D ring oscillators that operated rail-to-rail at VDD= 3V and maintained oscillation for VDD as low as 1.7V. These results demonstrate the potential for low VDD metal oxide-based integrated circuits fabricated in a low temperature budget, fully lithographic process for large-area transparent electronics.by Annie I. Wang.Ph.D

Threshold voltage in pentacene field effect transistors with parylene dielectric

Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 59-63).Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device.by Annie I. Wang.M.Eng.and S.B