Search for supersymmetry with a dominant R-parity violating LQDbar couplings in e+e- collisions at centre-of-mass energies of 130GeV to 172 GeV

A search for pair-production of supersymmetric particles under the assumption that R-parity is violated via a dominant LQDbar coupling has been performed using the data collected by ALEPH at centre-of-mass energies of 130-172 GeV. The observed candidate events in the data are in agreement with the Standard Model expectation. This result is translated into lower limits on the masses of charginos, neutralinos, sleptons, sneutrinos and squarks. For instance, for m_0=500 GeV/c^2 and tan(beta)=sqrt(2) charginos with masses smaller than 81 GeV/c^2 and neutralinos with masses smaller than 29 GeV/c^2 are excluded at the 95% confidence level for any generation structure of the LQDbar coupling.Comment: 32 pages, 30 figure

Search for Bs0B^{0}_{s} oscillations using inclusive lepton events

A search for Bs oscillations is performed using a sample of semileptonic b-hadron decays collected by the ALEPH experiment during 1991-1995. Compared to previous inclusive lepton analyses, the prop er time resolution and b-flavour mistag rate are significantly improved. Additional sensitivity to Bs mixing is obtained by identifying subsamples of events having a Bs purity which is higher than the average for the whole data sample. Unbinned maximum likelihood amplitude fits are performed to derive a lower limit of Dms>9.5 ps-1 at 95% CL. Combining with the ALEPH Ds based analyses yields Dms>9.6 ps-1 at 95% CL.A search for B0s oscillations is performed using a sample of semileptonic b-hadron decays collected by the ALEPH experiment during 1991-1995. Compared to previous inclusive lepton analyses, the proper time resolution and b-flavour mistag rate are significantly improved. Additional sensitivity to B0s mixing is obtained by identifying subsamples of events having a B0s purity which is higher than the average for the whole data sample. Unbinned maximum likelihood amplitude fits are performed to derive a lower limit of Deltam_s>9.5ps^-1 at 95% CL. Combining with the ALEPH D-s based analyses yields Deltam_s>9.6ps^-1 at 95% CL

Combined Forward-Backward Asymmetry Measurements in Top-Antitop Quark Production at the Tevatron

The CDF and D0 experiments at the Fermilab Tevatron have measured the asymmetry between yields of forward- and backward-produced top and antitop quarks based on their rapidity difference and the asymmetry between their decay leptons. These measurements use the full data sets collected in proton-antiproton collisions at a center-of-mass energy of $\sqrt s =1.96$ TeV. We report the results of combinations of the inclusive asymmetries and their differential dependencies on relevant kinematic quantities. The combined inclusive asymmetry is $A_{\mathrm{FB}}^{t\bar{t}} = 0.128 \pm 0.025$. The combined inclusive and differential asymmetries are consistent with recent standard model predictions

Research and Development for Near Detector Systems Towards Long Term Evolution of Ultra-precise Long-baseline Neutrino Experiments

With the discovery of non-zero value of $\theta_{13}$ mixing angle, the next generation of long-baseline neutrino (LBN) experiments offers the possibility of obtaining statistically significant samples of muon and electron neutrinos and anti-neutrinos with large oscillation effects. In this document we intend to highlight the importance of Near Detector facilities in LBN experiments to both constrain the systematic uncertainties affecting oscillation analyses but also to perform, thanks to their close location, measurements of broad benefit for LBN physics goals. A strong European contribution to these efforts is possible

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

ATLAS detector at the Large Hadron Collider (LHC) will undergo a major Phase-II upgrade for the High Luminosity LHC (HL-LHC). The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module (GCM) as a building block of its design. To achieve a high input and output bandwidth and substantial processing power, the GCM will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at high data rates (up to 28 Gb/s), a Global Trigger Technological Demonstrator board has been designed and tested. The main hardware blocks of the board are the Xilinx Virtex Ultrascale+ 9P FPGA and a number of optical modules, including high-speed Finisar BOA and Samtec FireFly modules. Long-run link tests have been performed for the Finisar BOA and Samtec FireFly optical modules running at 25.65 and 27.58 Gb/s respectively. Successful results demonstrating a good performance of the optical modules when communicating with the FPGA have been obtained. The paper provides a hardware overview and measurement results of the Technological Demonstrator

Global Trigger Versatile Module for ATLAS Phase-II upgrade

The ATLAS detector at the Large Hadron Collider will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses an ATCA Global Common Module as a building block of its design. The additional, standalone, Global Trigger Versatile Module has been designed according to the Global Trigger hardware specifications. The Global Trigger Versatile Module acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger in projects requiring high bandwidth and processing capabilities. To achieve a high input and output bandwidth and substantial processing power the Global Trigger Versatile Module hosts an advanced Xilinx Ultrascale+ VU13P FPGA and Finisar BOA optical modules, running at high data rates up to 25.8 Gb/s, as well as other hardware resources needed for the Global Trigger, located on a high-density PCB, optimized for high-speed data transmission. A testing program of the Global Trigger Versatile Module includes verification of the main hardware functionality of the module, performance evaluation of the high-speed optical modules and the FPGA, and Global Common Module development firmware tests. Successful results demonstrating a good performance of the on-board components have been obtained

Global Trigger Versatile Module for ATLAS Phase-II upgrade

ATLAS detector at the Large Hadron Collider (LHC) will undergo a major Phase-II upgrade for the High Luminosity LHC (HL-LHC). The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module (GCM) as a building block of its design. An additional Global Trigger Versatile Module (GVM) has been designed according to the Global Trigger hardware specifications. To achieve a high input and output bandwidth and substantial processing power, both the GVM and the GCM host the most advanced FPGAs and optical modules, running at high data rates (up to 28 Gb/s) as well as other hardware resources needed for the Global Trigger. The GVM acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger. The GVM is designed in an ATCA form factor with the possibility of a standalone operation. The main building blocks are the following: one large processing FPGA (Xilinx Ultrascale+ VU13P), up to eight Finisar BOA modules for real-time data path, one Finisar BOA module for interface to Front-End Link eXchange (FELIX) system, one UltraZed board with Zynq UltraScale+, one IPM Controller (IPMC), one FPGA power mezzanine and two DDR4 RAMs. In order to optimize the signal integrity for the high-speed signals, dedicated high-speed PCB design techniques, such as physical and spacing constraints, phase tuning, micro and buried vias, were used. Successful results demonstrating a good performance of the on-board components have been obtained. The poster will provide a hardware overview and measurement results of the GVM