Stability oriented SRAM performance optimization in subthreshold operation

International audienceIn this work we are analyzing the 6T SRAM cell operation in subthreshold in 32nm UTBB-FDSOI technology. The set of accurate equations describing the subthreshold SRAM cell behaviour in read and write are presented. Using these equations, the optimum tradeoffs between cell transistors VTs for best stability in subthreshold for read and retention are illustrated revealing write stability as the main limiting factor for low VDD operation. The analysis of write assist technique efficiency reveals, that setting the bitline voltage -0.1V gives the write μ/σ=5.66, while maintaining read μ/σ>9. The magnitude of write assist technique application can be further limited by modifying the VTs of SRAM cell transistors by increasing initial write stability while maintaining read μ/σ>6

Experimental 5G New Radio integration with VLC

International audienceIn this paper, integration of 5G New Radio (5G NR) with a Visible Light Communication (VLC) downlink architecture is proposed. This scheme combines two complementary wireless technologies: upcoming 5G NR and VLC to offer indoor enhanced wireless hybrid access able to provide each User Equipment (UE) with very high data rate and positioning support. The data transmission of the 5G NR frame over VLC has been implemented. This represents a novel approach to transmitting 5G NR over VLC by hardware experimentation based on Universal Software Radio Peripheral (USRP). The experiment results show that the proposed scheme with Quadrature Phase Shift Keying (QPSK) mapping achieves a data rate of 14.4 M bits/s and an Error Vector Magnitude (EVM) of 4.78% for a 55 cm free space transmission span

On improving the accuracy of Visible Light Positioning system using deep autoencoder

International audienceDC-biased optical Orthogonal Frequency DivisionMultiplexing (DCO-OFDM)-based visible light positioning (VLP)technology along with the Received Signal Strength(RSS) po-sitioning algorithm is widely used to achieve centimeter levelpositioning accuracy for incoming 5G era, especially indoorenvironment. However, the DCO-OFDM has the peak-to-averagepower ratio (PAPR) issue which imposes the nonlinear distortionand it will directly affect the positioning accuracy in the VLPsystem. The PAPR reduction scheme is urgently needed. There-fore, in this paper, the impact of PAPR reduction scheme onpositioning accuracy is investigated. The positioning accuracywith and without the selected mapping (SLM)-based PAPRreduction method are compared. The preliminary simulationresults show that the positioning accuracy has been improvedby 7.07 cm after using the SLM-based PAPR reduction method

The spice book

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Etude de l'impact de la variabilité process sur les circuits numériques

Concevoir un circuit numérique en technologie CMOS inferieur à 100nm se heurte à de multiples défis en termes de variation de process, voltage et temperature. L attention s est portée essentiellement sur les variations inter-die qui forme la plus grande partie des variations de process. Dans cette étude, nous nous sommes attachés sur deux formes particulières de variations : les divergences Inter-die NMOS a PMOS et les divergences aléatoires Intra-die local . Aucune d elles n avait jusqu alors d effet notable durant les conceptions industrielles et sont désormais toutes deux source de soucis majeurs. Le travail en academia se concentre principalement sur le changement de process ou sur les améliorations architecturales. Notre action s est orientée vers l amélioration de la conception au niveau porte logique et au niveau chemin. Notre attention s est portée sur les systèmes synchrones, i.e. system de distribution d horloge qui est fortement impacté par ces variations. Nous avons proposé quelques méthodes de conception et des stratégies d optimisation pour fabriquer des circuits plus robustes. La plupart de ces méthodes sont exploitables au sein même du flot de design existant ce qui minimise le cout et permet son adoption rapide dans l industrie. Nous avons inclus l effet des changements de voltage et de température sur ces deux variations pour élaborer une compréhension globale. Nous avons aussi proposé des méthodes pour vérifier les bases de notre travail en le comparant vis à vis des résultats de test sur silicium. Les résultats de ce travail ont permis de façonner la politique de comment gérer les divergences locales dans la conception industrielle.Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on interdie variations that form the bulk of process variations. In this work, we have focused on two particular kinds of variations- Inter-die NMOS to PMOS mismatch and Intra-die local random mismatch. Neither had a noticeable effect in industrial designs and has become a cause of worry only recently. The source of these variations lies in the basic process and is random in nature. Thus, their effect cannot be ameliorated without overhauling the complete process. The work in academia has mostly focused on process changes or architectural improvements. Our work is geared towards design improvements at gate and path level. We looked at the basic phenomena behind these variations and using simulations observed how they affect the different parameters in a digital design. The focus was on synchronous systems, i.e. clock distribution system that is highly impacted by these variations. We proposed some design methods and optimization strategies to make the circuits more robust. Most of these methods are exploitable within existing design flows that minimizes the cost and allows for quick adoption in the industry. We included the effect of voltage and temperature changes on these two variations to put together a comprehensive understanding. We also proposed methods to verify the basis of our work by comparing against silicon test results. The results of this work have helped to shape the policy of how to handle local mismatch in industrial designs.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF

An SNM Estimation and Optimization Model for ULP sub-45nm CMOS SRAM in the Presence of Variability

International audienceThis paper presents an universal optimization model for Static Noise Margin (SNM) of Ultra Low Power (ULP) CMOS SRAMs in the presence of statistical variations. Distributions of retention and read SNM derived analytically, are analyzed as a function of the threshold voltages of the N and PMOS devices. The proposed model implemented in Matlab is applied to optimize yield by maximizing the mean/6σ of SNM in the presence of local statistical VT variation of 3σ

Cryogenic CMOS Circuits and Systems: Challenges and Opportunities in Designing the Electronic Interface for Quantum Processors

Quantum computing could potentially offer faster solutions for some of today's classically intractable problems using quantum processors as computational support for quantum algorithms [1]. Quantum processors, in the most frequent embodiment, comprise an array of quantum bits (qubits), the fundamental computational unit of a quantum computer. Unlike conventional bits, qubits can take a coherent state ranging from |0 > to |1 > on a continuous sphere, known as the Bloch sphere (Figure 1). When the state of the qubit, represented by a vector on the Bloch sphere, is on the equator of such a sphere, qubits are said to be in maximum superposition. Entanglement is the second important quantum mechanical property of qubit states, where knowing the state of one qubit implies knowing the state of the other one as well

Tunnel FET Based Ultra-Low-Leakage Compact 2T1C SRAM

International audienceIn this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low leakage below 1fA/bit is achieved in the proposed design. Read and write cycle times of sub-2ns and sub-4ns are designed

Tunnel FET Based Refresh-Free-DRAM

International audienceA refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275$\mu$m$^2$ is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal