Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage

Scan-Chain Intra-Cell Aware Testing

This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46% on average) and a shorter test time (i.e., 42.20% on average) than by straightforwardly using an ATPG which directly targets these defects

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

International audienceIn-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase

Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation

International audienceIn this work, we used a commercial charge-coupled device (CCD) camera to detect and monitor terrestrial cosmic rays at ground level. Multi-site characterization has been performed at sea level (Marseille), underground (Modane Underground Laboratory) and at mountain altitude (Aiguille du Midi-Chamonix Mont-Blanc at +3,780 m of altitude) to separate the atmospheric and alpha particle emitter's contributions in the CCD response. An additional experiment at avionics altitude during a long-haul flight has been also conducted. Experiment results demonstrate the importance of the alpha contamination in the CCD response at ground level and its sensitivity to charged particles. Experimental data as a function of CCD orientation also suggests an anisotropy of the particle flux for which the device is sensitive. A complete computational modeling of the CCD imager has been conducted, based on a simplified 3D CCD architecture deduced from a reverse engineering study using electron microscopy and physico-chemical analysis. Monte Carlo simulations evidence the major contribution of low energy (below a few MeV) protons and muons in the CCD response. Comparison between experiments and simulation shows a good agreement at ground level, fully validated at avionics altitudes with a much higher particle flux and a different particle cocktail composition

Contribution au test et à la fiabilité des systèmes sur puce

Ce document présente la synthèse de mes travaux de recherche et d’enseignement effectués depuis septembre 1998, date à laquelle j’ai débuté ma thèse de doctorat. Les travaux de recherche ont été effectués au LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier) au sein du département de Microélectronique. Les activités d’enseignement ont été menées à la Faculté des sciences (ex UFR) / département EEA (Electronique, Electrotechnique et Automatique) de l’Université Montpellier 2 au niveau Licence et Master

Test intégré des circuits digitaux (analyse et génération de séquences aléatoires adjacentes)

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

A Comprehensive Learning-Based Flow for Cell-Aware Model Generation

International audienceAs the semiconductor industry continues to shrink the transistor feature size, new fault models need to be invented and deployed to ensure manufacturing test and diagnostic of the highest quality. The Cell-Aware (CA) test and diagnosis methodology targets the detection of defects inside standard (std) cells, at the transistor level. While becoming an industry standard, the CA methodology, has a large and costly deployment overhead, involving numerous analog simulations. In [1], we presented an innovative flow using Machine-Learning (ML) to reduce the CA test method runtime and ease its adoption for industrial usage. Experiments using different technology nodes demonstrated an over 99% runtime reduction for 80% of combinational cells. In this paper, new elements are presented to more widely take advantage of the ML flow for CA characterization. This includes a new decision algorithm, leveraging ML techniques to decide whether the CA characterization of a new std cell should be MLbased or simulation-based, thus allowing to decrease the CA characterization runtime while maintaining high quality CA models for all cells. Experimental results demonstrate the high performance of the new decision algorithm. The fault coverage on real cell-internal defects of ATPG patterns using ML predicted CA data proves that our predicted CA data can accurately replace those obtained by running extensive analog simulations, thus proving the effectiveness and pertinence of the proposed methodology

A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications

International audienceBrain-inspired computing architectures, brought by Artificial Neural Networks (ANNs), are an attractive solution to reduce the energy consumption of the conventional von Neumann's computation, with an excellent parallel processing capability. Therefore, critical applications, such as Space & Satellite, which impose severe constraints in terms of power consumption and computing efficiency, are excellent candidates to embed such networks. Nonetheless, integrated circuits operating during long-term and cumulative exposure to incidence levels of ionizing radiation may have their physical components degraded, thus drastically reducing their reliability and expected lifetime. A possible solution to enhance the radiation hardening characteristics of a conventional bulk CMOS device is to use the non-standard gate geometry referred to as Enclosed Layout Transistor (ELT). In this work, we propose to harden the design of an existing OxRAM-based neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180 nm technology, have been carried out to validate our proposed design. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications

An Advanced Diagnosis Flow for SRAMs

International audienc