Metal-semimetal Schottky diode relying on quantum confinement

Quantum confinement in a semimetal thin film such as bismuth (Bi) can lead to a semimetal-to-semiconductor transition which allows for the use of semimetals as semiconductors when patterned at nanoscale lengths. Bi native oxide on Bi thin film grown by molecular beam epitaxy (MBE) is investigated using X-ray photoelectron spectroscopy (XPS) to measure the elemental composition of the oxide. Also, an in-situ argon plasma etch step is developed allowing for the direct coating of the surface of thin Bi films by a metal contact to form a Schottky junction. Model structures of rhombohedral [111] and [110] bismuth thin films are found from density functional theory (DFT) calculations. The electronic structure of the model thin films is investigated using a GW correction and the formation of an energy band gap due to quantum confinement is found. Electrical characterization of the fabricated Bi-metal Schottky diode confirms a band gap opening in Bi thin film for a film thickness of approximately 5 nm consistent with the theoretical calculations

Organo-arsenic molecular layers on silicon for high-density doping

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 x 10²⁰ atoms cm⁻³. Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials

Surface doping and stabilisation of alternative CMOS material systems

Current electronic devices are built by employing numerous materials and a diverse array of fabrication processes. Semiconductors are the main building block which are used to create transistors. For the past 50 years, the size of a transistor has halved every 18-24 months, in accordance with Moore’s Law, allowing the semiconductor industry to pack more of them into a single chip, which has resulted in a significant increase in the processing power of computers over this period. However, this scaling of the transistor cannot continue indefinitely due to material limitations when dev ice sizes reach the order of only a few hundred atoms; this has led to the definition from the International Technology Roadmap for Semiconductors (ITRS) of key technical challenges and requirements to sustain this scaling by going More Moore. Some of the most interesting challenges include implementation of high-mobility CMOS materials, for example by introducing Ge or III-V compounds as channel materials, as well as scaling of Si (and its alternatives) CMOS, for which it will be necessary to tackle numerous issues such as parasitic control and gate stack engineering. The introduction of alternative CMOS channel materials comes with a wide array of problems, as each material comes with its set of advantages and disadvantages. Ge CMOS has higher intrinsic mobility than Si, both for n-type and p-type carriers, but n-channel implementation is challenging due to source-drain doping and contacting issues. III-V materials in general lack good mobility for p-type carriers and therefore would need to be integrated together for example with Ge, even if this then adds to the complexity of the whole process. As already mentioned, in addition to these integration challenges there is a whole set of scaling issues that must be addressed. In order to successfully continue scaling devices down and meet performance requirements, a wide array of process and material innovations will be needed, particularly as we transition from planar transistor, to finFET and gate-all-around (GAA) architectures which come with some manufacturing challenges. One of such challenges is the engineering of the transistor junction by conformal doping, in which the dopant addition must be precisely controlled, both spatially and quantitatively. Monolayer doping (MLD) has the potential to satisfy these needs as it allows for precise dopant control, due to its intrinsic self-limiting nature, while also being inherently conformal as it relies on surface reactions between a dopant molecule and a target surface. Chapters 3& 4 of the thesis describe the application of MLD on high-mobility alternative channel materials, such as germanium and gallium nitride. Another challenge identified by the ITRS for future devices is the overall reduction of processes and materials used in device fabrication in order to simplify the whole process flow. For example, the implementation of a monolithic material CMOS n- and p-channel would simplify process and material requirements as there would be no need to engineer different gate dielectrics or gate metals for different channels. Bismuth has recently been shown as a potential material for the formation of monolithic transistors in which the source, drain and channel are all made of the same material and where thickness can be used as the knob to tune the electrical properties of each element of the device. This would in turn allow to greatly reduce the number of steps in the channel fabrication, thus reducing integration complexity. However, bismuth readily passivates in air and forms a surface oxide which can potentially hinder further processing steps. Chapter 5 of this thesis focuses on a novel method for the removal of the oxide and the subsequent bare bismuth surface passivation which then allows for ambient handling of the now stabilised material