Accelerated Aging System for Prognostics of Power Semiconductor Devices

Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices

Effect of Electrostatic Discharge on Electrical Characteristics of Discrete Electronic Components

This article reports on preliminary results of a study conducted to examine how temporary electrical overstress seed fault conditions in discrete power electronic components that cannot be detected with reliability tests but impact longevity of the device. These defects do not result in formal parametric failures per datasheet specifications, but result in substantial change in the electrical characteristics when compared with pristine device parameters. Tests were carried out on commercially available 600V IGBT devices using transmission line pulse (TLP) and system level ESD stress. It was hypothesized that the ESD causes local damage during the ESD discharge which may greatly accelerate degradation mechanisms and thus reduce the life of the components. This hypothesis was explored in simulation studies where different types of damage were imposed to different parts of the device. Experimental results agree qualitatively with the simulation for a number of tests which will motivate more in-depth modeling of the damage

Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices, especially their failure modes as they age with nominal usage or sudden fault development is critical in ensuring efficiency. In this paper, a prognostics based health management of power MOSFETs undergoing accelerated aging through electrical overstress at the gate area is presented. Details of the accelerated aging methodology, modeling of the degradation process of the device and prognostics algorithm for prediction of the future state of health of the device are presented. Experiments with multiple devices demonstrate the performance of the model and the prognostics algorithm as well as the scope of application. Index Terms Power MOSFET, accelerated aging, prognostic

System level ESD protection

This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection.  It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.   • Provides a systematic approach for on-chip ESD protection design for system-level IC pins; • Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure; • Includes a comprehensive description of wafer- level and component-level test methodologies and numerical simulations

РОЗВИТОК ОБЛАДНАННЯ РОЗПОДІЛЬНИХ ПРИСТРОЇВ ТЯГОВОГО ЕЛЕКТРОПОСТАЧАННЯ. ЧАСТИНА І

It’s presented review of state and development technologies, technical parameters and characteristics modern basic type equipment in the distributive devices for traction power supply systems: complete block technologies, high-voltage switches direct and alternating current, powerand converting transformers, switchgears, recuperators and inverters, power supply automation. On example world's leading specimens shows possibilities high energy efficiency and reliability modern equipment for switchgears. Specifics main features and differences, advantages anddisadvantages of perspective equipment electric power supply systems are considered. It’s focused view on technical solutions other than those, used in Ukraine, to analyze the feasibility their development and implementation in the present conditions. General directions and criteria for choice rational strategy modernization distributive devices of traction power supply systems are determined. Analysis will allow performing selection technical parameters for devices in design mathematical models and subsequent verification, coordination and implementation in new devices, their compatibility with existing traction power system, railways, subwaysРассмотрено текущее состояние развития технологий, а также техническиепараметры и характеристики современного типового оборудования распределительных устройств систем тягового электроснабжения. Выделено специфику основных сходных черт и различий, преимуществ и недостатков перспективного оборудования систем электроснабжения. Сосредоточено внимание на технических решениях, отличных от тех,что применяются в Украине, с целью анализа целесообразности их развития и внедрения в нынешних условияхРозглянуто поточний стан розвитку технологій, а також технічні параметри та характеристики сучасного типового обладнання розподільних пристроїв систем тягового електропостачання. Виокремлено специфіку основних подібних рис і відмінностей, переваг і недоліків перспективного обладнання систем електропостачання. Зосереджено увагу на технічних рішеннях, відмінних від тих, що застосовуються в Україні, з метою аналізу доцільності їх розвитку та впровадження в теперішніх умовах

Miscorrelation Between Air Gap Discharge And Human Metal Model Stresses Due To Multi-Finger Turn-On Effect

Operation of NLDMOS-SCR devices under the human metal model (HMM) and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, whereas both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such dependence has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40 ns

Study Of Power Arrays In Esd Operation Regimes

The self-protection capability of arrays as a layout dependent parameter have been studied using a novel 2.5D simulation methodology. Several topology elements are identified to improve HBM robustness of the arrays. The physical effects responsible for local burnout are demonstrated based upon simulation tool capability

Self-Protection Capability Of Integrated Nldmos Power Arrays In Esd Pulse Regimes

This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data. © 2011 Elsevier Ltd. All rights reserved

2.5-Dimensional Simulation For Analyzing Power Arrays Subject To Esd Stresses

A new simulation-based methodology for analyzing the ESD performance of snapback multi-finger power arrays subject to ESD stress is developed and presented. The methodology utilizes a combination of a newly available 2.5-dimensional netlist extraction tool, ESD cell snapback compact model, and standard simulation CAD tools. Simulated snapback behavior and current distribution of power cells are demonstrated. © 2009 ESDA