Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades

MAPS in 130 nm triple well CMOS technology for HEP applications

Deep N-well CMOS monolithic active pixel sensors (DNWMAPS) represent an alternative approach to signal processing in pixellated detectors for high energy physics experiments. Based on different resolution constraints, two prototype MAPS, suitable for applications requiring different detector pitch, have been developed and fabricated in 130 nm triple well CMOS technology. This work presents experimental results from the characterization of some test structures together with TCAD and Monte Carlo simulations intended to study the device properties in terms of charge diffusion and charge sharing among pixels

Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end

A Pixel Read-Out Front-End in 28 nm CMOS with Time and Space Resolution

Future high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance

Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

Enhanced Logic Performance with Semiconducting Bilayer Graphene Channels

Realization of logic circuits in graphene with an energy gap (EG) remains one of the main challenges for graphene electronics. We found that large transport EGs (>100 meV) can be fulfilled in dual-gated bilayer graphene underneath a simple alumina passivation top gate stack, which directly contacts the graphene channels without an inserted buffer layer. With the presence of EGs, the electrical properties of the graphene transistors are significantly enhanced, as manifested by enhanced on/off current ratio, subthreshold slope and current saturation. For the first time, complementary-like semiconducting logic graphene inverters are demonstrated that show a large improvement over their metallic counterparts. This result may open the way for logic applications of gap-engineered graphene.Comment: Accepted by ACS Nan

Ice core chemistry database: an Antarctic compilation of sodium and sulfate records spanning the past 2000 years

Changes in sea ice conditions and atmospheric circulation over the Southern Ocean play an important role in modulating Antarctic climate. However, observations of both sea ice and wind conditions are limited in Antarctica and the Southern Ocean, both temporally and spatially, prior to the satellite era (1970 onwards). Ice core chemistry data can be used to reconstruct changes over annual, decadal, and millennial timescales. To facilitate sea ice and wind reconstructions, the CLIVASH2k (CLimate Variability in Antarctica and the Southern Hemisphere over the past 2000 years) working group has compiled a database of two species, sodium [Na+] and sulfate [SO2− 4 ], commonly measured ionic species. The database (https://doi.org/10.5285/9E0ED16E-F2AB4372-8DF3-FDE7E388C9A7; Thomas et al., 2022) comprises records from 105 Antarctic ice cores, containing records with a maximum age duration of 2000 years. An initial filter has been applied, based on evaluation against sea ice concentration, geopotential height (500 hPa), and surface wind fields to identify sites suitable for reconstructing past sea ice conditions, wind strength, or atmospheric circulation