Cell motility in confinement: a computational model for the shape of the cell

While cells typically tend to spread their cytoplasm in a flat and thin lamellipodium when moving on a flat substrate, it is widely observed that the cytoplasm has a compact shape in micro-channels, tending to fulfill the cross-section of the microchannel. We propose a minimal mathematical model for a 2D test case which describes the cell lamellipodium deformations when confined in a channel. We then go through a numerical investigation of this mathematical model and show that it allows to recover qualitatively the physiological characteristics of the confined cell

Cell motility in confinement: a computational model for the shape of the cell

International audienceWhile cells typically tend to spread their cytoplasm in a flat and thin lamellipodium when moving on a flat substrate, it is widely observed that the cytoplasm has a compact shape in micro-channels, tending to fulfill the cross-section of the microchannel. We propose a minimal mathematical model for a 2D test case which describes the cell lamellipodium deformations when confined in a channel. We then go through a numerical investigation of this mathematical model and show that it allows to recover qualitatively the physiological characteristics of the confined cell.Alors que les cellules ont généralement tendance à présenter un cytoplasme étendu en un large lamellipode extrêmement fin lors du déplacement sur un substrat plat, il est communément observé que le cytoplasme prend une forme compacte lors du déplacement dans des micro-canaux, remplissant au possible le volume contenu dans le micro-channel. Nous proposons un modèle mathématique minimal pour un cas test en 2D qui décrit les déformations du lamellipode en confinement. Nous proposons une exploration numérique de ce modèle mathématique et nous montrons qu’il permet de retrouver qualitativement les caractéristiques physiologiques de la cellule confinée

Integrated switched-capacitor-based cold-start circuit for DC-DC energy harvesters with wide input/output voltage range and low inductance in 40-nm CMOS

\u3cp\u3eThis paper outlines an integrated switched-capacitor (SC)-based cold-start circuit for dc-dc energy harvesters that uniquely combines a low cold-start voltage, wide input/output voltage and low inductance value in the boost stage. The proposed design specifically targets size-constrained, self-powered Internet-of-Things applications. The proposed design is an SC circuit built from low-threshold-voltage devices operating in the sub-threshold region and provides the drive voltage for high-threshold-voltage devices of the boost dc-dc converter. The SC circuit is an NMOS-based Dickson charge pump driven synchronously with a series of cross-coupled voltage doublers and voltage multiplying gate drivers. The SC circuit, which is integrated together with a boost converter as the dc-dc energy harvester, has been implemented in a 40-nm CMOS process for future system-on-chip integration. The measured results show that with a 4.7 μH boost converter inductance, the design can start up from typical input voltages as low as 190 mV while offering up to 2.4 V input and 5 V output voltage compatibility.\u3c/p\u3

Challenges in data‐based degradation models for lithium‐ion batteries

This work summarizes the findings resulting from applying an aging modeling approach to four different capacity loss experimental datasets of lithium ion batteries (LIBs). This approach assumes that the degradation trajectory of the capacity is a function of three variables: time, a kinetic constant, and a time dependent factor. The analysis shows that the time dependent factor is cell chemistry dependent, and cannot be averaged for calendar and cycling modes, and combined modes. This factor was also found to be a function of the stress factors. A quadratic model was used to obtain the kinetic constants per test, and statistical metrics were provided to evaluate the quality of the fitting, which was significantly affected when using averaged values of and re fitted kinetic constants. A set of test matrices is proposed for calendar, cycling, and mixed aging modes to overcome the challenges of data based models developed from accelerated test approaches for modeling aging in LIBs. This work also proposes a methodology to develop these data based aging models.The authors would like to thank Havelaar Canada and the Natural Sciences and Engineering Research Council of Canada (NSERC) for their financial support towards this research, and the University of Toronto Electric Vehicle (UTEV) Research Centre. Additionally, we would like to thank Prof. Torbjörn Thiringer and Dr. Evelina Wikner from Chalmers University of Technology in Göteborg, Sweden, for providing us their aging data

A GaN HEMT driver IC with programmable slew rate and monolithic negative gate-drive supply and digital current-mode control

This work presents an intelligent driver IC for 400 V GaN-based Power Factor Correction (PFC) applications. The targeted power level of the converter is 100 W, with a switching frequency above 500 kHz. The IC was implemented in a 140 nm automotive BCD SOI process, while the GaN HEMT and Schottky diode were optimized in a Si-fab compatible GaN-on-Si process. A low-Ron DMOS is integrated in the driver IC to achieve high-speed cascode switching operation. The chip also features a novel dual-mode drive scheme with monolithic negative drive voltage capability and programmable slew rate, as well as a digital peak current-mode controller. Advanced digital PFC control schemes can therefore be implemented, while EMC performance and efficiency can be optimized through active slope control