On the Degrees of freedom of the K-user MISO Interference Channel with imperfect delayed CSIT

This work investigates the degrees of freedom (DoF) of the K-user multiple-input single-output (MISO) interference channel (IC) with imperfect delayed channel state information at the transmitters (dCSIT). For this setting, new DoF inner bonds are provided, and benchmarked with cooperation-based outer bounds. The achievability result is based on a precoding scheme that aligns the interfering received signals through time, exploiting the concept of Retrospective Interference Alignment (RIA). The proposed approach outperforms all previous known schemes. Furthermore, we study the proposed scheme under channel estimation errors (CEE) on the reported dCSIT, and derive a closed-form expression for the achievable DoF with imperfect dCSIT.Comment: Draft version of the accepted manuscript at IEEE ICASSP 1

Retrospective Interference Alignment for the MIMO Interference Broadcast Channel

The degrees of freedom (DoF) of the multiple-input multiple-output (MIMO) Interference Broadcast Channel (IBC) with 2 cells and 2 users per cell are investigated when only delayed channel state information is available at the transmitter side (delayed CSIT). Retrospective Interference Alignment has shown the benefits in terms of DoF of exploiting delayed CSIT for interference, broadcast and also for the IBC. However, previous works studying the IBC with delayed CSIT do not exploit the fact that the users of each cell are served by a common transmitter. This work presents a four-phase precoding strategy taking this into consideration. Assuming that transmitters and receivers are equipped with $M,N$ antennas, respectively, new DoF inner bounds are proposed, outperforming the existing ones for $\rho = \frac{M}{N} > 2.6413$.Comment: 1 copyright page + 5 paper pages + 3 appendix pages, Submitted to IEEE ISIT 201

Retrospective Interference Alignment for the 3-user MIMO Interference Channel with delayed CSIT

The degrees of freedom (DoF) of the 3-user multiple input multiple output interference channel (3-user MIMO IC) are investigated where there is delayed channel state information at the transmitters (dCSIT). We generalize the ideas of Maleki et al. about {\it Retrospective Interference Alignment (RIA)} to be applied to the MIMO IC, where transmitters and receivers are equipped with $(M,N)$ antennas, respectively. We propose a two-phase transmission scheme where the number of slots per phase and number of transmitted symbols are optimized by solving a maximization problem. Finally, we review the existing achievable DoF results in the literature as a function of the ratio between transmitting and receiving antennas $\rho=M/N$. The proposed scheme improves all other strategies when $\rho \in \left(\frac{1}{2}, \frac{31}{32} \right]$.Comment: Draft version of the accepted manuscript at IEEE ICASSP 1

Achievable DoF-delay trade-offs for the K-user MIMO interference channel with delayed CSIT

©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The degrees of freedom (DoFs) of the K-user multiple-input multiple-output (MIMO) interference channel are studied when perfect, but delayed channel state information is available at the transmitter side (delayed CSIT). Recent works have proposed schemes improving the DoF knowledge of the interference channel, but at the cost of developing transmission involving many channel uses (long delay), thus increasing the complexity at both transmitter and receiver side. This paper proposes three linear precoding strategies, limited to at most three phases, based on the concept of interference alignment, and built upon three main ingredients: delayed CSIT precoding, user scheduling, and redundancy transmission. In this respect, the interference alignment is realized by exploiting delayed CSIT to align the interference at the non-intended receivers along the space-time domain. Moreover, a new framework is proposed where the number of transmitted symbols and duration of the phases is obtained as the solution of a maximization problem, and enabling the introduction of complexity constraints, which allows deriving the achievable DoF as a function of the transmission delay, i.e., the achievable DoF-delay trade-off. Finally, the latter part of this paper settles that the assumption of time-varying channels common along all the literature on delayed CSIT is indeed unnecessary.Peer ReviewedPostprint (author's final draft

Beamforming Coordination Techniques in OFDM Multi-hop Cellular Networks

English: Design and evaluate multi-hop cellular networks assuming coordination among multiantenna base stations and relay stations using linear precoders .Castellano: Diseñar y evaluar redes celulares multisalto asumiendo coordinación entre estaciones base y repetidores multiantena usando precodificadores lineales .Català: Dissenyar i avaluar xarxes cel·lulars multisalt assumint coordinació entre estacions base i repetidors multiantena fent servir precodificadors lineals

A Brief Description of the NMP ISA and Benchmarks

The Near Memory Processor (NMP) is a multithreaded vector processor integrated with the memory controller. The NMP works subordinately upon requests from the main processors. The NMP is complementary to the conventional superscalar processors and it is optimized for the bandwidth bounded applications and bit manipulation workloads. A program addressable memory in the NMP, Scratchpad provides an effectively large register set to hold vectors, streams and frequently accessed values. Avoiding saving and restoring the vector registers during context switch, the scratchpad reduces the overhead of the multithreading and enables a simple NMP architectural design. We design an instruction set that includes vector, streaming and bit manipulation instructions. We present the instruction set architecture of the NMP in this report, including register sets, addressing mode and instruction formats. A brief description of the benchmarks is also included

A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads

Many important scientific and engineering applications execute sub-optimally on current commodity processors and servers. Specifically, since they frequently use caches ineffectively, they are often heavily bottlenecked by global memory bandwidth. In addition, they sometimes need to perform expensive bit manipulation operations that are not efficiently supported by commodity ISAs. Moreover, an analysis of technology trends suggests that, despite the criticality of some of these applications, future commodity processors and servers are unlikely to be tuned for them. To address this problem, this paper proposes the design of a simple co-processor on which the main processor can off-load vector, streaming, and bit-manipulation computation. The co-processor is a blocked-multithreaded narrow in-order core with support for vectors, streams, and bit manipulation. It has no caches and a high bandwidth to memory. For this reason, rather than for its actual physical location, we call it Near-Memory Processor (NMP). Our simulations show that a set of scientific applications run much faster on the NMP than on an aggressive conventional processor. Specifically, the speedups obtained reach 18, with a geometric mean of 5.8 for 10 applications