Die Krise des Finanzmarkt-Kapitalismus : Herausforderung für die Linke

A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.The original publication is available at www.springerlink.com:Timmy Sundström and Atila Alvandpour, A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS, 2010, Analog Integrated Circuits and Signal Processing, (64), 3, 215-222.http://dx.doi.org/10.1007/s10470-009-9391-xCopyright: Springer Science Business Mediahttp://www.springerlink.com

Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters

The scaling of CMOS technologies has increased the performance of general purposeprocessors and DSPs while analog circuits designed in the same process have not been ableto utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has tooffer. This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters andtheir lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for lowaccuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results. The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power. The concept of low‐accuracy components is taken to its edge in the second ADC which oes not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity

Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components

The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs. However, analog circuits designed in the same process have not been able to utilize the scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. Integration of the system components on the same die means that the analog-to-digital converters (ADCs) needs to be implemented in the newest technologies in order to utilize the digital capabilities at these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of the potential that process has to offer. As the technology scales to smaller feature sizes, the possible sample-rate of ADCs can be increased. This thesis explores the design of high-speed ADCs and investigates architectural and circuit concepts that address the problems associated with lower supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is investigated and lower bounds, as set by both thermal noise and minimum feature sizes are formulated. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital correction or calibration, which leads to a reduction in power dissipation. Through the aid of new techniques and concepts, the power dissipation of low-to-medium resolution ADCs benefit from going to more modern CMOS processes, which is supported by both theory and published results. New architectures and circuits of high-speed ADCs are explored in test-chips based on the flash and pipeline ADC architectures. Two flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies. The first flash ADC is based on redundancy in the comparator array, allowing the use of low-accuracy, small-sized and low-power comparators to achieve an overall low-power solution. The flash ADC achieves 4.0 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC further explores the use of low-accuracy components, relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s and dissipates 23 mW of power, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity. In two implemented pipeline ADCs, the potential of very high sample-rates and energy efficiency is explored. The first pipeline ADC utilizes a new high-speed currentmode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous stateof-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. The second pipeline ADC relies on an inverter-based amplifier, used in switched-capacitor feedback in order to keep the amplifier biased at a poweroptimal point. The amplifier uses asymmetrically biased transistors in order to better match the p- and n-type transistors, which increases linearity and allows for fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits and the power dissipation was 73 mW. This shows that it is possible to achieve low power dissipation while maintaining both high sample-rates and medium resolution

A comparison of circuit implementations from a security perspective

In the late 90's research showed that all circuit implementations were susceptible to power analysis and that this analysis could be used to extract secret information. Further research to counteract this new threat by adding countermeasures or modifying the nderlaying algorithm only seemed to slow down the attack. There were no objective analysis of how different circuit implementations leak information and by what magnitude. This thesis will present such an objective comparison on five different logic styles. The comparison results are based on simulations performed on transistor level and show that it is possible to implement circuits in a more secure and easier way than what has been previously suggested

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication