Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology

International audienceThe Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results

Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology

The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D; on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results

Probing the chiral magnetic wave with charge-dependent flow measurements in Pb-Pb collisions at the LHC

The Chiral MagneticWave (CMW) phenomenon is essential to provide insights into the strong interaction in QCD, the properties of the quark-gluon plasma, and the topological characteristics of the early universe, offering a deeper understanding of fundamental physics in high-energy collisions. Measurements of the charge-dependent anisotropic flow coefficients are studied in Pb-Pb collisions at center-of-mass energy per nucleon-nucleon collision v sNN = 5.02TeV to probe the CMW. In particular, the slope of the normalized difference in elliptic (v2) and triangular (v3) flow coefficients of positively and negatively charged particles as a function of their event-wise normalized number difference, is reported for inclusive and identified particles. The slope rNorm 3 is found to be larger than zero and to have a magnitude similar to rNorm 2, thus pointing to a large background contribution for these measurements. Furthermore, rNorm 2 can be described by a blast wave model calculation that incorporates local charge conservation. In addition, using the event shape engineering technique yields a fraction of CMW (fCMW) contribution to this measurement which is compatible with zero. This measurement provides the very first upper limit for fCMW, and in the 10-60% centrality interval it is found to be 26% (38%) at 95% (99.7%) confidence level

A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5×1.5 mm including a matrix of 32×32 pixels with a pitch of 15μm . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42μm2 and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

International audienceThe long term goal of the CERN Experimental Physics Department R&D on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D; on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment