Analog MOS integrated circuits

The goal was to design single-chip lowpass filters with constant group delay in the pass band and 60 dB minimum attenuation in the stop band. The desired 3 dB frequencies are (in Hertz) 2.5, 5, 10, 20, 40, 80, 160, and 320. A filter class that satisfies the constant delay (linear phase) requirement while providing quite a narrow transition band is the Bessel-Chebyshev filters. It was found that the 7th order Bessel-Chebyshev response satisfied the requirement of the filter

Mismatch-Shaped Pseudo-Passive Two-Capacitor DAC

A simple mismatch-shaping scheme is proposed for a two-capacitor DAC. Unlike in other mismatchshaping systems, the shaped error is generated by direct filtering of a well-defined bounded signal, which can be generated as white noise. The operation is closely related to a specific digital interpolation filter, but arbitrary properties of the overall interpolation characteristic can be assured. Simulations indicate that the scheme can be used for the realization of DACs with 16-bit linearity and SNR performance, with only 0.1 % capacitance accuracy. The DAC is pseudo-passive, i.e. an active element is required only to buffer the output signal. Hence, it is potentially a very low-power circuit, suitable for portable applications

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

Abstract An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve the dynamic range and to reduce the nonlinearity caused by mismatches in the multibit DAC. Keywords Audio Delta-sigma Switched-capacitor DAC SDW

Introduction to circuit synthesis and design/ Temes

viii, 598 hal.; 21 cm

A Switched-Capacitor Digital Capacitance Bridge

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