The goal was to design single-chip lowpass filters with constant group delay in the pass band and 60 dB minimum attenuation in the stop band. The desired 3 dB frequencies are (in Hertz) 2.5, 5, 10, 20, 40, 80, 160, and 320. A filter class that satisfies the constant delay (linear phase) requirement while providing quite a narrow transition band is the Bessel-Chebyshev filters. It was found that the 7th order Bessel-Chebyshev response satisfied the requirement of the filter

Temes, Gabor C.

English

NASA Technical Reports Server

Final Report: 
Analog MOS Integrated Circuits 
NASA-Ames Agreement No: NAG 2-360 
Starting Date: 7/1/1985 
Closing Date: 6/30/1988 
Principal Investigator: 
Prof. Gabor C. Temes 
Department of Electrical Engineering 
Boelter Hall Rm. 773 1 
UCLA 
Los Angeles, CA 90024 
(PASA-CR-l82$S9) A N A L O G  80s  llElIEGBATED 
C l B C U 1 i S  E i n a l  f iefort ,  1 3111. 1965 - 30 Juri. 
4588 ( C a l i f o r n i a  Univ-) 2C & C S C L  09c 
4189-1 5325 
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63/33 0174579  
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https://ntrs.nasa.gov/search.jsp?R=19890005954 2020-03-20T04:49:36+00:00Z
. .  
TABLE OF CONTENTS 
1.INTRODUCTION ............................. 1 
I1 . CASCADE SYNTHESIS ....................... 2 
A . Factorization of the transfer function . . . . . . . . . . . . .  2 
B . Pairing of poles and zeros .................... 3 
....................... 3 
. . . . . . . . . . . . . .  4 
E . Filter Sections ............................ 5 
. . . . . . . .  8 
111 . FABRICATION AND TEST REULTS . . . . . . . . . . . . .  11 
C . Ordering of the blocks 
D . Mapping to the discrete time domain 
F . Filter sections with reduced capacitor spread 
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18 
I. INTRODUCTION 
The goal of this project is to design single-chip low-pass filters with constant group delay in the 
pass band and 60 dB minimum attenuation in the stop band. The desired 3dB frequencies are (in 
Hz): 
2.5,5, 10,20,40, 80, 160, 320 
A filter class that satisfies the constant delay (linear phase) requirement while providing quite a 
narrow transition band is the Bessel-Chebyshev filters [l]. It was found that the 7th order 
Bessel-Chebyshev response satisfied the requirements of the filter. The filter transfer function is 
(1) 
(~2+8.329~)(~2+ 10.572)(s2+ 19.3 12) 
s7+28s6+378s5+3 1 50s4+17325s3+62370s2+135 135s+l35 135 
&(s) = K 
where K is a normalization constant so that H ( 0 )  = 1. The 3dB frequency (normalized) is at R = 
2.286. The denominator is the 7th order Bessel polynomial. The magnitude and phase plots of 
HuoR) are shown in figure 1. 
62dB 
3dB S n 
Figure 1. Loss and group delay of the 7th order Bessel-Chebyshev filter 
1 
The implementation was as a switched-capacitor (SC) network. These are sampled data systems, 
but the signal amplitude is not quantized [2]. The SC technique allows high order filters to be 
integrated on silicon with very good accuracy. The shape of the transfer function depends on the 
capacitor ratios which are quite precisely controlled. The frequency axis can be scaled by changing 
the system clock frequency. 
11. CASCADE SYNTHESIS 
The transfer function in equation (1) can be expressed as the product of lower order functions of s, 
namely bilinear and biquadratic functions. The desired transfer function is obtained when circuits 
realizing these simpler functions are cascaded. The rest of this section describes the design steps. 
pi. Factorization of the transfer function; 
The numerator of (1) is already factorized, the denominator can be factorized using the 
Newton-Raphson root-finding algorithm. The poles and zeros of (1) are given below: 
Po = -4.97 17869 
P1= -2.6856769+ j5.4206941 P4 = -2.6856769- j5.420694 1 
p 2  = -4.0701392+ j3.5171760 Ps = -4.0701 392- j3.5 17 1760 
P3 = -4.7582905+ j 1.7392861 P6 = -4.7582905- j 1.7392861 
zo= - 
z1 = j8.329 
z2=  j10.57 
z3 = j19.31 
z4= -j8.329 
zs = -j10.57 
z6 = - j19.31 
2 
Therefore, the transfer function can be decomposed into one bilinear and three biquadratic 
functions. 
J3. Pairing of poles and z a  
After we pair z,  and p ,  to form the bilinear factor, there remains the issue of pairing the remaining 
three complex conjugate pairs of poles with the three complex conjugate pairs of zeros. 
Out of the many possible pairings 0; poles and zeros some result in transfer functions that are less 
sensitive to element nonidealities of the actual circuit implementation. It is known that the 
magnitude of a bounded transfer function is not sensitive to element variations at the frequencies 
where it achieves its maximum [3]. Motivated by this property, we can define our objective in the 
pairing of poles and zeros as that the magnitude of the transfer function of each of the building 
blocks must be asflat as possible in the pass band of the filter [4]. 
The flattest blocks occur when the pole-zero pairs are (pl, zl), (p2, z2), (p3, z3). The Q factors of 
each block (pole) are as follows: 
Q1 = 1.126, (pi) 
Q2 = 0.661, (P2) 
Q3 = 0.532, (p3) 
C. Ordering of the blocks: 
As it is with the pairing of poles and zeros, different orderings of the blocks result in different 
sensitivities to the nonidealities in the implementation. The objective is again to have theflattest 
possible response in the pass band at the output of the each block . It turns out that the best 
ordering is (Po, zo)+(pl, zl)+(p2, ~ 2 ) + ( p 3 ,  z3). Let us define the transfer functions for each 
block: 
3 
1 
Hou(s) = ' s+4.9717869 
(s2+8 .3292) 
(s2+5.37 13538~+36.5967852) 
(s2+1 0.572) 
(s2+8.1402784~+28.9365601) 
(s2+19.3 12) 
(s2+9.5 165906s+25.6664902) 
Hl& = kl 
H2a(s) = k2 
H3u(s) = k3 
D. Mapping to the discrete time domain: 
We have dealt with the continuous-time frequency transfer function until now. We use the bilinear 
mapping to the discrete-time complex frequency, z, domain: 
s = Z A  
T z+l 
where T is the sampling period and the continuous- and discrete-time complex frequencies are 
respectively, 
From (6) we obtain 
oT/2  = arctan(rn/ 2) 
If fZ is very small then the relationship between o and i2 is almost linear. 
(7) 
Applying (6) to (2) through (5) gives the transfer functions to be realized. The numerical values 
4 I 
depend on the particular value of T. 
E. Filter sectiow 
We realized the filter as a cascade of one bilinear and three biquadratic sections. 
The circuit diagram of the bilinear filter section is shown in figure 2. 
Figure 2. The bilinear SC section. 
The transfer function in terms of the capacitor values is given below (CA is set to 1): 
The circuit diagram of the high-Q biquadramc filter section is shown in figure 3. 
5 
Figure 3. The high-Q biquadratic SC section. 
The transfer function in t e r n  of the capacitor values is given below (CA and C, are set to 1): 
c 5 z  2+( C1C3+-2C5)z+C5 
H1(z) = - Z2+(C2C3+C&2)Z+( 1-C3C4) 
The circuit diagram of the low-Q biquadratric filter sections is shown in figure 4. 
I I 
(9) 
Figure 4. The low-Q biquadratic SC section. 
6 
The transfer function in terns of the capacitor values is given below (CA and CB are set to 1): 
c5 22+ (C 1 c3 +- 2C5)2+ cs 
H2*3(z) = - (l+C4)22+(C2C3-C4-2)z+l 
The calculated capacitor values are such that when the clock frequency (1/T ) is 10 kHz, the 3 dB 
frquency is 40 Hz. The capacitors are also scaled for maximum dynamic range and minimum size. 
The resulting values are shown in Table 1. 
TABLE 1 
Capacitor values for 3 dB frequency at 40 Hz with 10 kHz clock 
Capacitor Value (in unit capacitors) 
High-Q Biquadratic Section 
Bilinear Section CA 35.58923 
C1 ' 1.0 
c2 2.0 
c3 2.0 
C1 1.0 
c2 1 .o 
c3 1 .o 
CA 7.28401 
CB 31.98662 
c4 13.34987 
c5 16.40688 
1st Low-Q Biquadratic Section CA 25.58748 
CB 10.68347 
C1 1 .o 
c2 1 .o 
c3 1 .o 
c4 1 .o 
c5 2.90374 
2nd Low-Q Biquadratic Section CA 33.72466 
CB 13.6255 1 
C1 1 .o 
c2 1 .o 
c5 1 .o 
c3 1 SO305 
c4 1 SO305 
7 
F. Filter sect ions with red- 
A second filter was designed to realize much lower passband edge frequencies with moderate clock 
speeds. We used capacitive voltage dividers to reduce the capacitor spread to realizable levels. The 
filter has 3 dJ3 loss at 2.5 Hz when operated with 10 kHz clock. 
The circuit diagrams for the filter sections with capacitive voltage dividers (T-sections) are shown 
in Figures 5 through 7. 
Figure 5. Bilinear section with voltage dividers. 
8 
m ClS Cl 
- -  - -  
c.4 I !  
Figure 6.  High-Q biquadratic section with voltage dividers. 
Figure 7. Low-Q biquadratic section with voltage dividers. 
The capacitor values are given in Table 2. 
9 
TABLE 2 
Capacitor values for 3 dB frequency at 2.5 Hz with 10 kHz clock 
Value Value 
Capacitor with T without T 
I 
Biiinear Section 23.19570 
High-Q Biquadratic Section 
1st Low-Q Biquadratic Section 
1 .o 
1 .o 
23.19570 
1.43863 
1.43863 
23.19570 
1.43863 
1.43863 
23.19570 
4.87619 
21.51080 
1 .o 
1 .o 
1 .o 
1 .o 
1 .o 
1 .o 
2 1.5 1080 
9.08509 
1 1.32699 
19.25835 
8.38634 
1 .o 
1 .o 
19.25835 
1.02497 
1.02497 
19.25835 
1 .o 
12.0 
19.25835 
1.02497 
2.17828 
21.51080 
21.51080 
584.42578 
1 .o 
2.0 
2.0 
114.64308 
505.73633 
1 .o 
1 .o 
1 .o 
21 3.59784 
266.30664 
409.40088 
178.27975 
1 .o 
1 .o 
1 .o 
1 .o 
46.30406 
10 
2nd Low-Q Biquadratic Section CA 
CB 
C1 
ClS 
c2 
c, 
c2T 
c3 
c3s 
c4 
c5 
CIT 
C3T 
26.28833 539.59912 
14.85170 152.42438 
1.18146 1 .o 
1.1 8 146 
26.28833 
1 .o 1 .o 
1.5 
26.28833 
1.70085 1 .o 
1.70085 
26.28833 
2.0 1 .o 
1.02569 10.52675 
As can be seen from Table 2, the overall capacitor area is reduced by a power of 2. 
111. FABRICATION AND TEST RESULTS 
Both of the designs were fabricated as a single chip using 5-pm double-poly CMOS process 
provided by MOSIS, a federal government supproted agency. We obtained the samples in March 
1988. Table 3 gives some of the physical properties of the fabricated chips: 
TABLE 3 
Some Physical Properties of the Fabricated Filter 
Technology: pwell CMOS, double poly 
Minimum feature size: 5 pm 
Chip size: 
Unit capacitor: 0.978 pF 
Power consumption: 280 mW 
Clock input: 
Package : 
6800 pm X 4595 pm 
(265 mil X 179 mil) 
Power supplies: k 5 V  
fi V square-wave with 50% duty cycle 
40 pin ceramic DIP 
The chip phograph is shown in Figure 8. 
The yield was somewhat low, around 50%. This could have been due to the large size of the chip 
by typical MOSIS standards. The frequency domain measurments were done using a network 
analyzer. The magnitude and phase response plots are provided at the end of the section. The 
11 
results for both sets of filters are in close agreement with the design values. Due to the limitations 
of the network analyzer the plots do not show the response in the 0 to 5 Hz range. Because of this 
limitation, the plots for the filter with the voltage dividers were obtained with 160 kHz clock 
frequency. 
The manual testing at DC showed that the filter with voltage dividers had quite high output offset 
voltage, around 0.8 V. But the other filter had much lower output offset, around 20 mV. We have 
found that the offset voltage can be reduced by adjusting the rising and falling times of the input 
clock signal. 
The filter that was designed to give 40 Hz passband edge at 10 kHz clock operated without 
problems for clock frequencies in the range 625 Hz to 100 KHz. 
12 
- .. , . -. . . . . - . .-. 
m 
U 
m 
P 
Q 
Q 
> O  
H *  
0 0  
\t.r 
J O  
0 
ll0 
w e  a 0  Y 
8 
Figure 9. Magnitude response of the 40 Hz design with 10 kHz clock. 
14 
> 
\ 
H n 
.I w > w 
.I 
IL w a 
N 
I 
0 
0 
0 
0 
0 
b 
wt 
Figure 10. Phase response of the 40 Hz design with 10 kHz clock. 
15 
rn 
0 
0 
P 
Nul 
I -  
Lo 
0 
0 
0 
> O  
H -  
m 0  
\ d  
J w 
> m  
w o  
J O  
0 
L O  w -  
E O  
Figure 1 1. Magnitude response of the 2.5 Hz design with 160 kHz clock. 
16 
N z 
0 
0 
0 
0 
0 
0 
It) 
0 
k 
Lo 
a 
e 
N 
I 
0 
0 
0 
in 
I- 
U 
4 
I- 
u) 
e 
Na3 
3:b 
U G  w w  
pr 
0) 
U 
0 
0 
0 
u) 
9 
0 
tn 
0)  
U 
0 
0 
a 
7 
L 
L 
f 
f 
N 
I 
0 
0 
rl 
n 
0 
I- cn 
Figure 12. Phase response of the 2.5 Hz design with 160 kHz clock. 
17 
REFERENCES 
[ 13 
[2] 
[3] 
[4] 
Feistel, V. K. H. and R. Unbehauen, "Tiefplsse mit Tschebyscheff-Character . . . , ' I  
Frequenz, vol. 19, pp. 265-282, 1965. 
Gregorian, R. and G. C. Temes, Analog MOS Integrated Circuits for Signal 
Processing, A Wiley-Interscience Publication, John Wiley & Sons, 1986. 
Orchard, H. J., "Inductorless filters," Electron. Lett., vol. 2, pp. 224-225, 1966. 
Sedra, A. S. and P. 0. Brackett, Filter Theory and Design: Active and Passive, pp. 
600, Matrix Publishers, Inc., 1978. 
18 


Analog MOS integrated circuits

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