3 research outputs found

    Clustered yield model for SMT boards and MCM's, A

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    Includes bibliographical references.This paper describes a clustered yield model for complex surface mount technology (SMT) assemblies and multichip modules (MCM's). Based on yield modeling techniques that have been proven in the manufacturing of integrated circuits (IC's), this model uses the negative binomial distribution of defects to calculate board yield after test. Manufacturing data validates that this model accurately predicts the clustering of defects and the yield predictions are significantly better than traditional binomial models

    Sensitivity analysis of critical parameters in board test

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    Includes bibliographical references (page 63).The authors analyze the main contributors to the quality and cost of complex boards. With manufacturing data from Hewlett-Packard boards, they use simulation models to derive the sensitivity of quality and cost to the solder defect rate, the functional defect rate, and test coverage. They also give a simple cost estimate of implementing IEEE 1149.1 boundary scan on ASICs. Their new yield model, which accounts for solder defect clustering, provides highly accurate yield predictions

    Defects, Fault Coverage, Yield And Cost, In Board Manufacturing

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    An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett--Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced, and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given. 2.INTRODUCTION In designing complex high performance boards, one has to make several decisions. What Surface Mount Technology process should be used? What defect rate is tolerable in custom ASICs? Is IEEE 1149.1 boundary scan necessary? What levels of board test coverage are optimum? If these fundamental parameters in board manufacturing are not optimized properly, the profit margin of the product will shrink. If, on the other hand, products are designed..
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