Defects, Fault Coverage, Yield And Cost, In Board Manufacturing

Abstract

An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett--Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced, and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given. 2.INTRODUCTION In designing complex high performance boards, one has to make several decisions. What Surface Mount Technology process should be used? What defect rate is tolerable in custom ASICs? Is IEEE 1149.1 boundary scan necessary? What levels of board test coverage are optimum? If these fundamental parameters in board manufacturing are not optimized properly, the profit margin of the product will shrink. If, on the other hand, products are designed..