Fault Tolerant Nanosatellite Computing on a Budget

In this contribution, we present a CubeSat-compatible on-board computer (OBC) architecture that offers strong fault tolerance to enable the use of such spacecraft in critical and long-term missions. We describe in detail the design of our OBC’s breadboard setup, and document its composition from the component-level, all the way down to the software level. Fault tolerance in this OBC is achieved without resorting to radiation hardening, just intelligent through software. The OBC ages graceful, and makes use of FPGA-reconfiguration and mixed criticality. It can dynamically adapt to changing performance requirements throughout a space mission. We developed a proof-of-concept with several Xilinx Ultrascale and Ultrascale+ FPGAs. With the smallest Kintex Ultrascale+ KU3P device, we achieve 1.94W total power consumption at 300Mhz, well within the power budget range of current 2U CubeSats. To our knowledge, this is the first scalable and COTS-based, widely reproducible OBC solution which can offer strong fault coverage even for small CubeSats. To reproduce this OBC architecture, no custom-written, proprietary, or protected IP is needed, and the needed design tools are available free-of-charge to academics. All COTS components required to construct this architecture can be purchased on the open market, and are affordable even for academic and scientific CubeSat developers

Efficient residential gateway architecture for the support of integrated services

The thesis proposes a system architecture for residential gateways in the form of a Network Processor. The Residential Gateway is the device that integrates all home networks (Ethernet, LON, HPNA, etc) and in the same time provides Internet and PSTN access. The proposed architecture is configurable so as to allow the adoption of one, among a variety of different access technologies and interfaces. The thesis presents a board level implementation of a residential gateway. The system is analyzed and its problems and bottlenecks are encountered. In the second part of the document the problems that arose are overcome through the development of a SoC (System on Chip) that decentralizes protocol processing. Its architecture is innovative based on three major hardware blocks; the Protocol Processing units, the Header Processing unit and the specifically designed DMA controller. All the three operate in a pipelined fashion in order to provide lookups, data transfer and protocol processing in an efficient way, thus alleviating the central processor from time consuming operations

Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configuration frame but fail to correct upsets with higher multiplicity in a single frame caused by a single event. This phenomenon has been observed in modern commercial-off-the-shelf FPGAs. Bit interleaving schemes are used in some FPGA families to scatter the multiple upsets into more than one frame, but this does not fully resolve the problem of uncorrectable errors. In this article, we propose a configuration memory scrubbing approach for SRAM-based FPGA devices, which combines the embedded ECC logic with an interframe, interleaved parity code to build a mixed 2-D coding technique. The proposed technique improves the multiple-bit error correction capabilities of the on-chip ECC scheme while keeping the error correction latency and hardware cost low. The scrubbing concept has been validated under heavy-ion irradiation, where it succeeded in correcting all the single and multiple upsets observed during the radiation experiment

Single Event Effects Characterization of the Programmable Logic of Xilinx Zynq-7000 FPGA Using Very/Ultra High-Energy Heavy Ions

This article studies the impact of radiation-induced single-event effects (SEEs) in the Zynq-7000 field programmable gate array (FPGA) and presents an in-depth analysis of the SEE susceptibility of all the memories of the programmable logic. The radiation experiments were performed in the CERN North Area facility and in the GSI Helmholtz Centre for Heavy Ion Research using very/ultra high-energy heavy ions. The offline analysis of the radiation experimental results produced a deep understanding for various SEE phenomena observed in the Zynq-7000 FPGAs, such as single-event function interrupts (SEFIs), single-event transient (SET) in global signals, and multiple bit upsets that could be key issues for the design of an effective SEE mitigation approach