Soft error immune GaAs circuit technologies

The article of record as published may be found at http://dx.doi.org/10.1109/GAAS.1996.567901Cosmic radiation induced soft errors present a major difficulty for space applications that utilize digital GaAs circuits and systems. Techniques to reduce soft error sensitivity by 5 orders of magnitude or more, to sufficient levels for safe implemen[ta]tion of GaAs ICs in space applications are presented. These results show that the need for redundancy and error correction is eliminated. Space systems will benefit by reduced power and area requirements, plus a substantial improvement in system performance over present radiation hardened silicon-based technologies

Effects of low-temperature buffer-layer thickness and growth temperature on the SEE sensitivity of GaAs HIGFET circuits

The article of record as published may be found at http://dx.doi.org/10.1109/23.659049Heavy-ion Single Event Effects (SEE) test results reveal the roles of growth temperature and buffer layer thickness in the use of a low-temperature grown GaAs (LT GaAs) buffer layer for suppressing SEE sensitivity in GaAs HIGFET circuits.U.S. Navy Space and Naval Warfare System

A picosecond-response photoconductive-sampling probe for digital circuit testing

The article of record as published may be found at http://dx.doi.org/10.1109/LEOS.1997.645385Lasers and Electro-Optics Society Annual Meeting, 1997. LEOS '97 10th Annual Meeting. Conference Proceedings., IEEE (Volume: 2) Date of Conference: 10-13 Nov 1997 Page(s): 236 - 237 vol.2 Meeting Date : 10 Nov 1997-13 Nov 1997 Conference Location : San Francisco, CARecent efforts in noninvasive high-frequency and high-resolution measurement techniques have led to the development of a number of photoconductive probes [l-41]. In this paper the feasibility of using the fiber-coupled, micromachined probe described in [2,3] for in-circuit testing and characterization is demonstrated by detecting waveforms at internal nodes of two different digital circuits, On the one hand, measurements have been carried out which reveal the performance of a circuit under standard operating conditions. In this case the measured electrical signals originate from an external source, i.e., an rf synthesizer. In a second application, femtosecond optical pulses have illuminated one of the transistors of a circuit to generate the signal that is measured. This second approach is used to emulate so-called single-event upsets (SEU), which are usually caused by cosmic particles in satellite-based electronic systems. These effects have a negative impact on the performance and reliability of these systems and therefore are a limiting factor for their commercial implementation. In the past, optical techniques to generate SEU effects have been successfully demonstrated for testing single devices [5]. In contrast, the results presented here demonstrate the generation and detection of these effects inside a complex circuit environment. Thus, they may especially benefit the development of radiation-immune circuits

Single event upsets in gallium arsenide pseudo-complementary MESFET logic

The article of record as published may be found at https://doi.org/10.1109/23.488786An introduction to gallium arsenide (GaAs) Pseudo-Complementary MESFET Logic (PCML) circuits is presented. PCML was developed to reduce the sensitivity of high-speed GaAs logic to radiation-induced single event upsets (SEUs). Experiments for testing the single-event upset (SEU) sensitivity of GaAs PCML integrated circuits (ICs) are described. The results of the experiments are analyzed. This new type of high-speed, low-power, GaAs logic provides decreased sensitivity to SEUs compared to more traditional circuit designs such as Directly-Coupled FET Logic (DCFL). PCML is fully compatible with existing GaAs E/D MESFET fabrication processes, such as those commonly used to make DCFL

SEU design consideration for MESFETs on LT GaAs

The article of record as published may be found at http://dx.doi.org/101109/23.659047Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII{reg_sign} process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined

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