Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC

The design and the preliminary measurements of a prototype 10 bit pipeline ADC based on 1.5-bit per stage architecture, developed for the luminosity detector at International Linear Collider (ILC) are presented. The ADC is designed in two versions, with and without a sample-and-hold circuit (S/H) at the input. The prototypes are fabricated in 0.35 m CMOS technology. A dedicated test setup with a fast FPGA based data acquisition system (DAQ) is developed for the ADC testing. The measurements of static (INL, DNL) and dynamic parameters are performed to understand and quantify the circuit performance. The integral (INL) and differential (DNL) nonlinearity are below 1 LSB and 0.5 LSB respectively. The dynamic measurements show signal to noise (SNHR) ratio of about 58 dB for sampling frequency up to 25 MHz

High-Performance Near-Time Processing of Bulk Data

Enterprise Systems like customer-billing systems or financial transaction systems are required to process large volumes of data in a fixed period of time. Those systems are increasingly required to also provide near-time processing of data to support new service offerings. Common systems for data processing are either optimized for high maximum throughput or low latency. This thesis proposes the concept for an adaptive middleware, which is a new approach for designing systems for bulk data processing. The adaptive middleware is able to adapt its processing type fluently between batch processing and single-event processing. By using message aggregation, message routing and a closed feedback-loop to adjust the data granularity at runtime, the system is able to minimize the end-to-end latency for different load scenarios. The relationship of end-to-end latency and throughput of batch and message-based systems is formally analyzed and a performance evaluation of both processing types has been conducted. Additionally, the impact of message aggregation on throughput and latency is investigated. The proposed middleware concept has been implemented with a research prototype and has been evaluated. The results of the evaluation show that the concept is viable and is able to optimize the end-to-end latency of a system. The design, implementation and operation of an adaptive system for bulk data processing differs from common approaches to implement enterprise systems. A conceptual framework has been development to guide the development process of how to build an adaptive software for bulk data processing. It defines the needed roles and their skills, the necessary tasks and their relationship, artifacts that are created and required by different tasks, the tools that are needed to process the tasks and the processes, which describe the order of tasks

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade

We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25 μm technology and optimised for the short, 2.5 cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We have obtained the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in view of the minimization of the power consumption, as the upgrade detector may contain up to 70 million of channels. System tests with different power distribution schemes proposed for the future tracker detectors are possible with this chip. The ABCN-25 ASIC is now serving as the prototype readout chip in the developments of the modules and staves for the upgrade of the ATLAS Inner Detector

Measurements of Matching and High Count Rate Performance of Multichannel ASIC for Digital X-Ray Imaging Systems

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel-to-channel (sd/mean ap 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals

Measurement of shower development and its Moli\`ere radius with a four-plane LumiCal test set-up

A prototype of a luminometer, designed for a future e+e- collider detector, and consisting at present of a four-plane module, was tested in the CERN PS accelerator T9 beam. The objective of this beam test was to demonstrate a multi-plane tungsten/silicon operation, to study the development of the electromagnetic shower and to compare it with MC simulations. The Moli\`ere radius has been determined to be 24.0 +/- 0.6 (stat.) +/- 1.5 (syst.) mm using a parametrization of the shower shape. Very good agreement was found between data and a detailed Geant4 simulation.Comment: Paper published in Eur. Phys. J., includes 25 figures and 3 Table

Performance of fully instrumented detector planes of the forward calorimeter of a Linear Collider detector

Detector-plane prototypes of the very forward calorimetry of a future detector at an e+e- collider have been built and their performance was measured in an electron beam. The detector plane comprises silicon or GaAs pad sensors, dedicated front-end and ADC ASICs, and an FPGA for data concentration. Measurements of the signal-to-noise ratio and the response as a function of the position of the sensor are presented. A deconvolution method is successfully applied, and a comparison of the measured shower shape as a function of the absorber depth with a Monte-Carlo simulation is given.Comment: 25 pages, 32 figures, revised version following comments from referee

ECFA Detector R&D Panel, Review Report

Two special calorimeters are foreseen for the instrumentation of the very forward region of an ILC or CLIC detector; a luminometer (LumiCal) designed to measure the rate of low angle Bhabha scattering events with a precision better than 10$^{-3}$ at the ILC and 10$^{-2}$ at CLIC, and a low polar-angle calorimeter (BeamCal). The latter will be hit by a large amount of beamstrahlung remnants. The intensity and the spatial shape of these depositions will provide a fast luminosity estimate, as well as determination of beam parameters. The sensors of this calorimeter must be radiation-hard. Both devices will improve the e.m. hermeticity of the detector in the search for new particles. Finely segmented and very compact electromagnetic calorimeters will match these requirements. Due to the high occupancy, fast front-end electronics will be needed. Monte Carlo studies were performed to investigate the impact of beam-beam interactions and physics background processes on the luminosity measurement, and of beamstrahlung on the performance of BeamCal, as well as to optimise the design of both calorimeters. Dedicated sensors, front-end and ADC ASICs have been designed for the ILC and prototypes are available. Prototypes of sensor planes fully assembled with readout electronics have been studied in electron beams.Comment: 61 pages, 51 figure