FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA- 256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA- 256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design

High-Throughput of SHA-256 Hash Function with Unfolding Transformation

Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security application such as Keyed-Hash Message Authentication Code (HMAC), digital signature and others. There are different types of hash function such as MD5, SHA-1, RIPEMD-160, SHA-256, SHA-224, SHA-384, SHA-512 and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2 and SHA-256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and with factor 2 was superior in terms of maximum frequency and was better than the conventional SHA-256 design

High-Throughput of SHA-256 Hash Function with Unfolding Transformation

Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security application sllch as keyed-Hash Message Authentication Code (HMAC), digital signature and others. There are different types of hash function such as M05, SHA-l, RIPEMO-160, SHA-256, SHA-224, SHA-384, SHA-512 and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2 and SHA256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and with factor 2 was conventional SHA-256 design

The Impact of Soft Error On C-Element with Different Technology

This paper presents current injection resemble single event upset (SEU) current at the vulnerable nodes on Celements in particular Single Inverter with Inverter Latch (SIL) under two different technology 90nm and 180nm. C-element mainly uses in asynchronous circuits as the demand of consuming low power continue to become more important compared with synchronous circuits. However, one of the problems of asynchronous circuits is that they stay sensitive to SEU continuously for the whole cycle of operation. For asynchronous circuits, an acknowledgement signal is sent to the preceding register after the current operation is finished, indicating it is ready for the next operation. In the event of SEU hitting one of the registers, no acknowledgement signal is sent and therefore the preceding register does not assign the next operation to the current computational block. It is observed that the size of the transistor is the most important factors of critical charge variation since it has the highest standard deviation compared with temperature. This is due to the increasing the size of the transistors increases the gate capacitance from the output and therefore the collected charge needed to flip the output is also larger. However, as the size of the circuit is bigger, the probability of hitting by SEU is also increased even though the circuit is more resistant against SEU. The least significant factor is the temperature. As the temperature increased, the mobility of the carrier is reduced and degrades the performance of the transistor

Throughput Enhancement of the RIPEMD-160 Design Using the Unfolding Transformation Technique

Abstract: Many cryptographic applications use RIPEMD-160 hash functions, such as digital signatures, Hash Message Authentication Code (HMAC), and other data security applications. The suggested RIPEMD-160 designs are as follows: RIPEMD-160 iterative design, RIPEMD-160 unfolding with factor two, and RIPEMD-160 unfolding with factor four. These methodologies were applied to RIPEMD-160 designs in order to evaluate the inner structure of the design in terms of area, maximum frequency, and throughput. In this project, the RIPEMD-160 hash function was implemented with a high throughput utilising an unfolding transformation technique with a factor of four. The throughput of RIPEMD-160 unfolding design has been increased. The goal of the project is to improve the throughput of RIPEMD-160. The throughput of RIPEMD-160 was increased to around 1753.50 Mbps by applying the unfolding transformation factor four approach. When RIPEMD-160 unfolding with factor four designs is compared to other RIPEMD-160 designs, the percentage of performance to area ratio increases by 1.51%. In comparison to alternative designs, the results suggest that the proposed designs perform the best. ModelSim Altera-Quartus II simulation results were used to prove the accuracy of the RIPEMD-160 designs in terms of functional and timing simulations

High Speed and Throughput Evaluation of SHA-1 Hash Function Design with Pipelining and Unfolding Transformation Techniques

In recent years, designing of SHA-1 hash function has become popular because it was important in security design application. One of the applications of SHA-1 hash function was HMAC where the architecture of SHA-1 needed to be improved in terms of speed and throughput in order to obtain the highperformance design. The objective of this project was to design high speed and throughput evaluation of SHA-1 hash function based on a combination of pipelining and unfolding techniques. By using both techniques in designing the architecture of SHA- 1 design, the speed of SHA-1 hash function can be increased significantly as well as throughput of the design. In this paper, five proposed SHA-1 architectures were designed with different stages of pipelining such as 1, 4 and 40 stages. The results showed the high-speed design of SHA-1 design can be obtained by using 40 stages pipelining with unfolding factor two. This design provided a high-speed implementation with maximum frequency of 308.17 MHz on Arria II GX and 458.59 MHz on Virtex 5 XC5VLX50T. Furthermore, the throughput of the design also increased about 150.269 Gbps and 223.618 Gbps on Arria II GX and Virtex 5 XC5VLX50T respectively. Thus, highspeed design of SHA-1 hash function was successfully obtained which can give benefit to society especially in security system data transmission and other types of hash functions

Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

Some applications, such as Message Authentication Code (MAC), rely on different hashing operations. There are various hash functions, including Message-Digest 5 (MD5), RACE Integrity Primitives Evaluation Message Digest 160 (RIPEMD-160), Secure Hash Algorithm 1 (SHA-1), and Secure Hash Algorithm 256 (SHA-256), among others. The network layer is the third of seven layers of the Open Systems Interconnection (OSI) concept, also known as the Internet. It handles network addressing and physical data routing. Nowadays, enhanced internet security is necessary to safeguard networks from illegal surveillance. As a result, Internet Protocol Security (IPsec) introduces secure communication across the Internet by encrypting and/or authenticating network traffic at the IP level. IPsec is an internet-based security protocol. Encapsulating Security Payload (ESP) and Authentication Header (AH) protocols are separated into two protocols. The MAC value is stored in the authentication data files of the Authentication Header and Encapsulating Security Payload. This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. During data transfer, HMAC is critical for message authentication. It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. The accuracy of the HMAC design, which is based on the SHA-256 design, was examined and confirmedusing ModelSim. The results indicate that the maximum frequency of the HMAC-SHA-256 design is approximately 195.16 MHz

Design of Completion Detectors in Asynchronous Communication System

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulatio

Design and Implementation of Advanced Encryption Standard Using Verilog HDL

Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the exponential development of the Internet. One of the main concerns involving software implementation of encryption algorithm is the possibility of slower processing when transmitting and receiving data which consequently will encounter low security level during process of encryption for real-time application. The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. Real­time application is essential for today's modem world and Field Programmable Gate Array approach is applied for this purpose. The optimization approaches include loop release, pipeline architecture and Look-Up-Table (LUT) which allow for exact synchronization in order to meet applications' requirements in real time. The design is coded using the Verilog HDL and the hardware design is analyzed and tested with Altera Cyclone 11-V in Quartus II and ModelSim. Through comparative analysis with previous implementation, the maximum throughput for this design is 31.37 Gbit/s for the encryption process can operate at 244.89 MHz. The complete 128-bit AES encryption cycle requires only 41 clock cycles to get the encrypted data